K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.     

24 GHz low-noise amplifier in 0.18 /spl mu/m CMOS technology

A 24 GHz monolithic low-noise amplifier (LNA) is implemented in a standard 0.18 /spl mu/m CMOS technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 GHz. The input and output return losses are better than 11 dB and 22 dB across the 22-29 GHz span, respectively. The operation frequency of 24 GHz is believed to be the highest reported for LNA in a standard CMOS technology.     

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

带有ESD保护,900MHz/2.4GHz Dual-Band CMOS LNA的设计

设计了一个可以同时工作在900 MHz和2.4 GHz的双频带(Dual-Band)低噪声放大器(LNA).相对于使用并行(parallel)结构LNA的双频带解决方案,同时工作(concurrent)结构的双频带LNA更能节省面积和减少功耗.此LNA在900MHz和2.4 GHz两频带同时提供窄带增益和良好匹配.该双频带LNA使用TSMC 0.25 μm 1P5M RF CMOS工艺.工作在900MHz时,电压增益、噪声系数(Noise Figure)分别是21 dB、2.9 dB;工作在2.4 GHz时,电压增益、噪声系数分别是25dB、2.8 dB,在电源电压为2.5 V时,该LNA的功耗为12.5mW,面积为1.1mm×0.9 mm.使用新颖的静电防护(ESD)结构使得在外围PAD上的保护二极管面积仅为8 μm×8 μm时,静电防护能力可达2 kV(人体模型)     

5.7 GHz low-power variable-gain LNA in 0.18 /spl mu/m CMOS

A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 /spl mu/m CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.     

Circuit Topology Analysis of CMOS LNA in Mobile Communication Systems

1　Introduction　Now ,mostoftheLNAinRFreceiversarede signedwithGaAsorbipolartechnologies,whichhavealargepowerdissipationandunfavorableper formanceofintegration .CMOStechnologiestakeincreasinglyadvantagesoftechnologyadvances,whichhaveverylow powerconsumptionandmakepossibletheintegrationofcompletecommunicationsystems[1 ] .Forexample ,mobilecommunicationsystemreceiversemployextensivedigitalsignalpro cessingtoperformacquisition ,tracking ,anddecod ingfunctions.TheuseofCMOStechnologiesforimpl…     

A 24-GHz CMOS front-end

This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.     

3.6~4.7GHz低噪声放大器

以一种经典的窄带低噪声放大器结构为基础,分析级联放大器的S参数,通过优化元件参数,获得了一种在3.6~4.7 GH z范围内具有低输入回波损耗、低噪声系数的放大器。采用标准的0.18μm RF CM O S工艺进行了设计和实现。芯片面积为0.6 mm×1.5 mm。测试结果表明:在3.6~4.7 GH z的范围内,该宽带低噪声放大器输入回波损耗小于-14 dB;噪声系数小于2.8 dB,增益大于10 dB。在1.8 V电源下功耗约为45 mW。     

一种可切换的双频段CMOS低噪声放大器

基于0.18μm RF CMOS工艺,设计了一种可切换的双频段CMOS低噪声放大器,其输入输出均匹配到50Ω。加入封装、ESD电路和PAD模型,采用Cadence Spectre RF进行仿真。结果显示,在1.8 V工作电压下,1.575 GHz输入时,LNA的噪声系数、功率增益和偏置电流分别为0.9 dB、18.2 dB和5.7 mA;1.2 GHz输入时,LNA的噪声系数、功率增益和偏置电流分别为0.8dB、16.8 dB和5.3 mA。     

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

Packaged single-ended CMOS low noise amplifier with 2.3 dB noise figure and 64 dBm IIP/sub 2/

A single-ended low noise amplifier (LNA) implemented in a foundry 0.18 /spl mu/m CMOS process is tested on a PC board using the chip-on-board technique. The measured S/sub 11/ and S/sub 22/ are less than -10 dB over 5.15-5.35 GHz, which is the lower subband of UNII and HIPERLAN/2 band. The measured noise figure is 2.0 dB and power gain is 15.5 dB at 5.15 GHz, while drawing 5.8 mA of current from a 1.8 V supply. The measured IIP/sub 2/ is greater than 64 dBm. This extremely high IP/sub 2/ is due to the tuned response of the LNA. The LNA is suitable for WLAN applications in the lower UNII and HIPERLAN/2 subband.     

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm².     

深亚微米CMOS低噪声放大器的设计

通过一个符合性能指标的，用于射频接收系统的CMOS低噪声放大性能的设计，讨论了深亚微米MOSFET的噪声情况，并在满足增旋和功耗的前提下，对低噪声放大噪声性能进行分析和优化，该LNA工作在2.5GHz电源电压，直流功耗为25mW，能够提供19dB的增益（S21），而噪声系数仅为2.5dB，同时输入匹配良好，S11为-45dB，整个电路只采用了一个片外电感使电路保持谐振，此设计结果证明CMOS工艺在射频集成电路设计领域具有可观的潜力。     

A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

Design a novel 5.8 GHz wideband low noise amplifier in CMOS technology for WLAN applications

A novel complementary metal-oxide semiconductor (CMOS) low noise amplifier (LNA) was designed in this paper for wireless local area network (WLAN) applications in the 5.8?GHz ISM band. The LNA presents low voltage and low power dissipation design integrated in TSMC 0.18?µm standard CMOS technology and achieves a gain of 15.2?dB, a noise figure of 2.5?dB and an IIP3 of ?6.5?dBm with input return loss ?38.5?dB, output return loss of ?46.1?dB while dissipating just 4.96 mW from a 1V supply voltage.     

用于无线局域网的双频段低噪声放大器

采用0.18μmCMOS工艺设计并制造了一款新型的应用于无线局域网的双频段低噪声放大器。设计中,通过切换输入电感和负载电感,来使电路分别工作在2.4GHz和5.2GHz频段。在1.8V的电源电压下,在2.4GHz和5.2GHz两个频段上,其增益分别达到了11.5dB和10.2dB,噪声系数分别是3dB和5.1dB。芯片总面积是0.9mm×0.65mm。