24 GHz low-noise amplifier in 0.18 /spl mu/m CMOS technology

A 24 GHz monolithic low-noise amplifier (LNA) is implemented in a standard 0.18 /spl mu/m CMOS technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 GHz. The input and output return losses are better than 11 dB and 22 dB across the 22-29 GHz span, respectively. The operation frequency of 24 GHz is believed to be the highest reported for LNA in a standard CMOS technology.     

A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 /spl mu/m CMOS technology

A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-/spl mu/m CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the author's knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.     

Low-noise amplifier in 0.12 /spl mu/m standard CMOS technology for K-band

A K-band CMOS low-noise amplifier with a noise figure of 4.26 dB and a peak gain of 18.86 dB is presented. The low-noise amplifier has a peak gain frequency of 20.3 GHz and an input referred 1 dB compression point of -16 dBm. These are believed to be the lowest noise figure and highest gain values reported to date at these frequencies in a standard CMOS technology.     

W-band multiple-ring resonator by standard 0.18-/spl mu/m CMOS technology

A high-Q multiple-ring resonator fabricated by standard 0.18-/spl mu/m CMOS process is presented. This design achieves a high quality factor at W-band without the need of any post-processing steps. Simulation results indicate that the four open-loop rings enhance the quality factor by 120% compared with the resonator with a single ring. The measured quality factors are 38 and 83 at /spl sim/75GHz under the loaded and unloaded conditions, respectively.     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

Robust sound localization in 0.18 /spl mu/m CMOS

This paper presents a hardware implementation of a sound localization algorithm that localizes a single sound source by using the information gathered by two separated microphones. This is achieved through estimating the time delay of arrival (TDOA) of sound at the two microphones. We have used a TDOA algorithm known as the "phase transform" to minimize the effects of reverberations and noise from the environment. Simplifications to the chosen TDOA algorithm were made in order to replace complex operations, such as the cosine function, with less expensive ones, such as iterative additions. The custom digital signal processor implementing this algorithm was designed in a 0.18-/spl mu/m CMOS process and tested successfully. The test chip is capable of localizing the direction of a sound source within 2.2/spl deg/ of accuracy, utilizing approximately 30 mW of power and 6.25 mm/sup 2/ of silicon area.     

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

Performance of 1-10-GHz traveling wave amplifiers in 0.18-/spl mu/m CMOS

The authors present two four-stage traveling-wave amplifiers (TWA) fabricated in a 0.18-/spl mu/m CMOS process. A TWA with an internal drain bias network achieved a gain of 5 dB out to 10 GHz, and another TWA without an on-chip bias network achieved a gain of 8 dB out to 10 GHz. These are the highest frequency CMOS TWAs known to the authors.     

0.18 /spl mu/m CMOS backplane receiver with decision-feedback equalisation embedded

Decision-feedback equalisation (DFE) is explored to reduce intersymbol interference and crosstalks in high-speed backplane applications. In the design of the clock and data recovery circuit, embedding DFE within a phase and frequency detector enhances the recovery of data inherently from distorted input signals and facilitates providing DFE with the recovered clock.     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.     

5.7 GHz low-power variable-gain LNA in 0.18 /spl mu/m CMOS

A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 /spl mu/m CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.     

0.18 /spl mu/m CMOS dual-band UWB LNA with interference rejection

A CMOS dual-band ultra-wideband low noise amplifier (LNA) with interference rejection is presented. The proposed LNA employs a current reuse structure to reduce power consumption and an active notch filter to produce in-band rejection in the 5 GHz WLAN frequency band. The load tank of the current reuse stage is optimised to provide an additional out-band attenuation in the 2.4 GHz WLAN band. Measurement shows a peak gain of 19.7 dB in the low band (3-5 GHz) and 20.3 dB in the high band (6-10 GHz), while the in-band and out-band maximum rejections are 19.6 and 12.8 dB, respectively.     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

A matrix amplifier in 0.18-/spl mu/m SOI CMOS

A fully integrated matrix amplifier with two rows and four columns (2-by-4) fabricated in a three-layer metal 0.18-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. It exhibits an average pass-band gain of 15 dB and a unity-gain bandwidth of 12.5 GHz. The input and output ports are matched to 50 /spl Omega/ using m-derived half sections; the measured S/sub 11/ and S/sub 22/ values exceed -7 and -12 dB, respectively. Integrated in 2.0/spl times/2.9mm/sup 2/, it dissipates 233.4 mW total from 2.4- and 1.8-V power supplies.     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-/spl mu/m CMOS technology

The design and performance of two new miniature 360/spl deg/ continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-/spl mu/m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm /spl times/ 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm /spl times/ 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360/spl deg/ phase-control range above 5 GHz reported to date.