1.5 V tunable Square-Root Domain filter

A novel approach to the design of low-voltage CMOS Square-Root Domain filters is presented. It is based on the large-signal behaviour of a well-known class-AB linear transconductor. A first-order filter is built employing three such transconductors, featuring simplicity and compactness. Measurement results for an experimental prototype in 0.8 /spl mu/m CMOS validate the technique proposed. The filter operates with a single supply voltage of 1.5 V and can be tuned in more than one decade.     

A Modified CMOS Balanced Output Transconductor with Extended Linearity

A new CMOS balanced output transconductor is presented. The circuit is based on applying the dynamic biasing technique on the floating current source to extend its linearity range. The difference in the biasing currents is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for high frequency applications requiring a wide dynamic range. Rail-to-rail operation is achieved with THD of –33.64 dB. The bandwidth achieved by the transconductor is 240 MHz, and the supply voltage used is ±1.5 V.     

A <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript><Emphasis Type="Italic">-C</Emphasis> continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs

A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency of 10–20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8 V supply voltage.     

Low-voltage transconductor with high linearity and large bandwidth

A linear tunable CMOS transconductor is proposed which uses a new low-voltage supercascode transistor to provide a high output resistance. Using a standard 0.8 /spl mu/m CMOS technology, simulation results are provided that show the operation of the proposed transconductor with a 1.2 V peak-to-peak differential input signal and 1.5 V supply voltage. The proposed transconductor features a high linearity and more than 100 MHz bandwidth.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

A New IIP2 Enhancement Technique for CMOS Down-Converter Mixers

The design of a CMOS mixer for cellular phone and 3G applications is challenging because of tough linearity and noise requirements. A new technique for second-order input intercept point (IIP2) enhancement of CMOS down-converter mixers is introduced in this brief. The technique is based on canceling second-order intermodulation components generated in input pseudodifferential transconductor, by injecting a nonlinear current to the mixer. Since this current is controlled by a high bandwidth feedback loop, the cancellation technique can be used in multistandard mixers for high channel bandwidth applications like UMTS and IEEE802.11 as well as GSM. A CMOS mixer demonstrating the performance for UMTS standard is designed in a 65-nm technology which can work with supplies as low as 1 V. The simulation results show that the differential and common mode IIP2 of the mixer are improved about 22 and 29 dB, respectively, while cancellation circuit consumes less than 3.3 mA. The other mixer parameters such as noise figure are not affected by the proposed technique.     

Low‐Voltage Tunable Pseudo‐Differential Transconductor with High Linearity

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage‐to‐current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of ?67 dB at 1 MHz for an input of 1 V_pp and a supply voltage of 1.8 V.     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

Second-order intermodulation mechanisms in CMOS downconverters

An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

0.5 V CMOS inverter-based tunable transconductor

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master–slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.     

A New Linearized CCII-Based Fully Differential CMOS Transconductor Used for \hbox {G}_\mathrm{m}-C Active Filters Implementation

The paper presents a new linearized, of high performance, fully differential transconductor, based on class AB second generation current conveyor (CCII) in CMOS technology. The proposed circuit is composed by two positive CCII cells connected in series and a common mode feedback loop. Unlike other CMOS circuits on the basis of CCII reported in the literature, the proposed transconductor cell allows to obtain a higher transconductance value, an improved linearity and operates at high frequency for a 3.3 V supply voltage. As an application, the new transconductor cell in CMOS technology is used for designing a 4th order differential $\hbox {G}_\mathrm{m}$ -C low-pass filters in different approximations (Butterworth and Chebyshev) operating up to 300 MHz cut-off frequency. The simulations performed in 130 nm CMOS process confirm the theoretical results.     

Current-feedback source-degenerated CMOS transconductor with very high linearity

A highly linear current-feedback (CF) transconductor with resistive source-degeneration is developed in CMOS technology. It consists of a differential source follower cascaded with a classical source-degenerated transconductor with its drain current fed back to modulate the bias of the source follower for nonlinearity cancellation, yielding an overall linear transfer function in the circuit. Designed using a 0.35 /spl mu/m CMOS process for a continuous-time delta-sigma application, the CF transconductor achieves a total harmonic distortion better than -80 dB up to 1 MHz for a 0.8 V input differential voltage while the supply voltage is 2.5 V and the power consumption is 3.4 mW.     

A novel pseudo differential transconductor for IEEE 802.11 WLANs

A novel pseudo differential transconductor for multi-mode analog baseband channel selection filter is presented. The highly linear transconductor is designed based on the dynamic source degeneration and predistortion cancellation technique. Meanwhile, wide tuning range is achieved with the current division technique. An LC ladder third-order Butterworth low-pass filter implemented with transconductors and capacitors was fabricated by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency ranging from 4 to 20 MHz. The tuning range is wide enough for the specifications of IEEE 802.11a/b/g/n Wireless LANs under the consideration of low power consumption and linearity requirement. The maximum power consumption is 3.61 mA at the cutoff frequency of 20 MHz.     

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-/spl mu/m implementation achieves a SFDR of 68 dB and a THD of -66.5dB using a dual supply of /spl plusmn/1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion.     

A linear compact tunable transconductor for Gm-C applications

A CMOS highly linear voltage-controlled transconductor suitable for Gm-C filter design is presented. The control loop to program the transconductance maintains the input transistors in triode region with a compact topology. Measurement results for the transconductor fabricated in a 0.5-??m CMOS technology feature a spurious-free dynamic range (SFDR) of 72?dB for 1 V_pp differential inputs at 1?MHz. The voltage to current converter ensures a high linearity level for a wide transconductance range. Functionality of the transconductor is shown in a fifth-order Gm-C tunable complex filter well suited for a dual-mode Bluetooth/Zigbee transceiver.     

A high bandwidth constant gm and slew-rate rail-to-railCMOS input circuit and its application to analog cells for low voltageVLSI systems

A new rail-to-rail CMOS input architecture is presented that delivers behavior nearly independent of the common-mode level in terms of both transconductance and slewing characteristics. Feedforward is used to achieve high common-mode bandwidth, and operation does not rely on analytic square law characteristics, making the technique applicable to deep submicron technologies. From the basis of a transconductor design, an asynchronous comparator and a video bandwidth op amp are also developed, providing a family of general purpose analog circuit functions which may be used in high (and low) bandwidth mixed-signal systems. Benefits for the system designer are that the need for rigorous control of common-mode levels is avoided and input signal swings right across the power supply range can be easily handled. A further benefit is that having very consistent performance, the circuits can be easily described in VHDL (or other behavioral language) to allow simulation of large mixed-signal systems. The circuits presented may be easily adapted for a range of requirements. Results are presented for representative transconductor, op amp, and comparator designs fabricated in a 0.5 μm 3.3 V digital CMOS process     

Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors

In this paper, a biasing technique for cancelling second-order intermodulation (IM2) distortion and enhancing second-order intercept point (IIP2) in common-source and common-emitter RF transconductors is presented. The proposed circuit can be utilized as an RF input transconductor in double-balanced downconversion mixers. By applying the presented technique, the achievable IIP2 of the mixer is limited by the linearity of the switching devices, component mismatches, and offsets. The proposed circuit has properties similar to the conventional differential pair transconductor in that it ideally displays no IM2 distortion. However, the presented circuit is more suitable for operation at low supply voltages because it has only one device stacked between the transconductor input and output. In the conventional differential pair, two devices consume the voltage headroom. The noise performance of the proposed transconductor is similar to the noise performance of the traditional common-source (emitter) and differential pair transconductors at given bias and device dimensions. On the other hand, the third-order intercept point (IIP3) of the presented transconductor is slightly higher than the IIP3 of the differential pair transconductor at given bias. Finally, the proposed circuit can also be employed as a current mirror, the ratio of which is very insensitive to the voltage swings at the gate or base of the current mirrored transistor.     

A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor

This paper presents a new CMOS transconductor providing low distortion for rail-to-rail signals. The circuit is based on using the anti-phase common source topology with the floating current source to extend its linearity range. The difference in the biasing currents of the floating current source is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for applications requiring wide dynamic ranges. Rail-to-rail operation is achieved with THD less than –37 dB. The bandwidth achieved by the transconductor is 67.5 MHz using a supply voltage of ±1.5 V.     

A CMOS transconductor with 80-dB SFDR up to 10 MHz

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80-dB spurious-free dynamic range (SFDR) for 3.6-V_pp differential inputs up to 10 MHz. The combination of resistors at the input and negative feedback around the operational transconductance amplifier (OTA) allows this transconductor to accommodate a differential input swing of 4 V with a 3.3-V supply. The total harmonic distortion (THD) of the transconductor is -77 dB at 10 MHz for a 3.6-V_pp differential input and third-order intermodulation spurs measure less than -79 dBe for 1.8-V_pp differential inputs at 1 MHz. The transconductance core dissipates 10.56 mW from a 3.3-V supply and occupies 0.4 mm² in a 0.35-μm CMOS process