Quantum mechanical device modeling: FinFET having an isolated n+/p+ gate region strapped with poly-silicon

In this paper, we present our numerical study on FinFET having an isolated n+/p+ gate region strapped with metal and poly-silicon structure. Our theoretical work is based on 2-D quantum-mechanical simulator with a self-consistent solution of Poisson-Schr?dinger equation. Our numerical simulation revealed that the threshold voltage (VT) is controlled within -0.1 approximately +0.2 V with varying the doping concentration of the n+ and p+ polysilicon gate region from 1.0 x 10(17) to 1.0 x 10(18) cm(-3). We also confirmed that the better VT tolerance of the FinFET on the variation of the fin thickness can be expected over the conventional FinFET structure. For instance, the VT of the FinFET under this work exhibited 0.02 V tolerance with respect to the variation of the fin thickness change of 5 nm (from 30 to 35 nm) while the traditional FinFET demonstrates the tolerance of 0.12 V for the same variation of the fin thickness.     

Formation and simulation of a thermally stable NiSi FUSI gate electrode by a novel integration process

The low resistivity nickel fully silicided (FUSI) gate have received increasing attention over the past several years due to the simply integration scheme for implementation and ease of passivation of the underlying gate dielectric for sub-65 nm/45 nm CMOS devices. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. In order to obtain a thermally stable Ni-FUSI gate electrode, we developed a unique integration process to achieve NiSi phase stabilize at temperature 900 °C and delay the agglomeration of NiSi. For the first time, we established an effective way to identify the phase transformations by some nondestructive techniques such as X-ray diffraction, sheet resistance measurement and AFM analysis. The correlations between its electrical and morphological changes during Ni-Si phase transformation were presented. F-incorporation demonstrated some improvements in both morphology and phase stability of the NiSi films at high processing temperatures. Furthermore, modeling the effect of dopants in NiSi on nano-sizes MOSFETs devices was implemented by ISE-TCAD. A low threshold voltage can be tuned by pre-doping the poly-Si with Sb for sub-45 nm NFET devices.     

Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed

Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si channels by controlled solid-state conversion of Ge/Si NWs to NiSixGe y alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious short-channel effects present in lithographically defined sub-100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drain-source bias of 0.5 V yield transconductance values of 78 and 91 microS, respectively, and maximum on-currents of 121 and 152 microA. The scaled transconductance and on-current values for a gate and bias voltage window of 0.5 V were 6.2 mS/microm and 2.1 mA/microm, respectively, for the 40 nm device and exceed the best reported values for planar Si and NW p-type FETs. In addition, analysis of the intrinsic switching delay shows that terahertz intrinsic operation speed is possible when channel length is reduced to 70 nm and that an intrinsic delay of 0.5 ps is achievable in our 40 nm device. Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub-100 nm Ge/Si NWFETs with integrated high-kappa gate dielectric operate near the ballistic limit.     

On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.     

3-D Monte Carlo Simulation of the Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double Gate MOSFETs

For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon body and the gate dielectric becomes significant, producing appreciable body thickness fluctuations. These fluctuations result in a scattering potential related to the quantum confinement variation within the channel which, similarly to the interface roughness scattering, influences the mobility, the drive current and the intrinsic parameter variations. In this paper we have developed an ensemble Monte Carlo simulation approach to study the impact of quantum confinement scattering on the transport in sub-10 nm UTB DG MOSFETs, and the corresponding intrinsic parameter variations. By comparing the Monte Carlo simulations with drift-diffusion simulations we quantify the important contribution of the quantum confinement related scattering to the current fluctuations in such devices     

Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology

In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography.     

Application of Cat-CVD for ULSI technology

The ULSI technology has been following Moore's law into the sub-100 nm era, although several challenging technical issues must be resolved. This paper describes possible application of Cat-CVD for ULSI technology beyond the 45 nm node. Especially, Cat-CVD SiN film for a transistor gate sidewall and/or a pre-metallic liner layer, and removal of photo resist (ash) by Cat-induced hydrogen atoms in the interconnect structure with an extreme low-k material are mainly discussed.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

The Influence of Fin Shape on the Amplitude of Random Telegraph Noise in the Subthreshold Regime of a Junctionless FinFET

Technical Physics Letters - The dependence of random telegraph noise (RTN) amplitude on the gate overdrive in a junctionless field-effect transistor (FinFET) with rectangular and trapezoidal...     

Sensitivity of Multigate mosfets to Process Variations–-An Assessment Based on Analytical Solutions of 3-D Poisson's Equation

This paper investigates the sensitivity of multigate MOSFETs to process variations using analytical solutions of 3-D Poisson's equation verified with device simulation. FinFET and Tri- gate with both heavily doped and lightly doped channels have been examined regarding their immunity to process-induced variations and dopant number fluctuation. Our study indicates that lightly doped FinFET has the smallest threshold voltage (V_th) dispersion caused by process variations and dopant number fluctuation. For heavily doped devices, dopant number fluctuation may become the dominant factor in the determination of overall V_th variation. The V_th dispersion of Tri-gate may therefore be smaller than that of FinFET because of its better immunity to dopant number fluctuation.     

Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowering, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire FinFETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.     

Study of sintering behavior of vapor forms of 1-octanethiol coated copper nanoparticles for application to ink-jet printing technology

Sub-50 nm copper nanoparticles coated with sub-5 nm 1-octanethiol layer for oxidation inhibition were examined to confirm the 1-octanethiol removal temperature as the sub-50 nm copper nanoparticles are sintered. As a result, 1-octanethiol Self-Assembled Multi-layers (SAMs) on sub-50 nm copper nanoparticles were successfully removed before sintering of copper nanoparticles so that a high density of copper line could be obtained. Finally, the line resistivity was measured and compared to verify the effect of sintering in different atmospheres. As a result, electrical resistivity of the copper pattern sintered in hydrogen atmosphere was measured at 6.96 x 10(-6) ohm-cm whereas that of the copper pattern sintered in mixed gas atmosphere was measured at 2.62 x 10(-5) ohm-cm. Thus, sintering of copper patterns was successfully done to show low electrical resistivity values. Moreover, removal of 1-octanethiol coating after sintering process was confirmed using X-ray photoelectron spectroscopy (XPS) analysis. By showing no sulfur content, XPS results indicate that 1-octanethiol is completely removed. Therefore, the vapor form of 1-octanethiol coating layers can be safely used as an oxidation inhibition layer for low temperature sintering processes and ink-jet applications.     

Assessment of high-frequency performance limits of graphene field-effect transistors

High frequency performance limits of graphene field-effect transistors (FETs) down to a channel length of 20 nm have been examined by using self-consistent quantum simulations. The results indicate that although Klein band-to-band tunneling is significant for sub-100 nm graphene FETs, it is possible to achieve a good transconductance and ballistic on-off ratio larger than 3 even at a channel length of 20 nm. At a channel length of 20 nm, the intrinsic cut-off frequency remains at a few THz for various gate insulator thickness values, but a thin gate insulator is necessary for a good transconductance and smaller degradation of cut-off frequency in the presence of parasitic capacitance. The intrinsic cut-off frequency is close to the LC characteristic frequency set by graphene kinetic inductance (L) and quantum capacitance (C), which is about 100 GHz·μm divided by the gate length.      

Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

Extrinsic resistance due to contacts and nonabrupt lateral extension doping profile can become a performance-limiter in ultrathin body double-gate FETs (DGFET). In this paper, two-dimensional device simulations are used to study and optimize the extrinsic resistance in a sub-20 nm gate length DGFET. For a given lateral doping gradient, the extension doping needs to be offset from the gate edge by an amount called the underlap. The current drive, and hence transistor performance, is maximized when the underlap is chosen in such a way as to balance the impact of nonabrupt doping on the short channel effects and series resistance. This optimization depends upon the maximum allowed off-state subthreshold leakage current and the electrostatic integrity of the device structure.     

A Sub-10 nm Vertical Organic/Inorganic Hybrid Transistor for Pain-Perceptual and Sensitization-Regulated Nociceptor Emulation

Pain-perceptual nociceptors (PPN) are essential sensory neurons that recognize harmful stimuli and can empower the human body to react appropriately and perceive precisely unusual or dangerous conditions in the real world. Furthermore, the sensitization-regulated nociceptors (SRN) can greatly assist pain-sensitive human to reduce pain sensation by normalizing hyperexcitable central neural activity. Therefore, the implementation of PPNs and SRNs in hardware using emerging nanoscale devices can greatly improve the efficiency of bionic medical machines by giving them different sensitivities to external stimuli according to different purposes. However, current most-normal organic/oxide transistors face a great challenge due to channel scaling, especially in the sub-10 nm channel technology. Here, a sub-10 nm indium-tin-oxide transistor with an ultrashort vertical channel as low as ≈3 nm, using sodium alginate bio-polymer electrolyte as gate dielectric, is demonstrated. This device can emulate important characteristics of PPN such as pain threshold, memory of prior injury, and pain sensitization/desensitization. Furthermore, the most intriguing character of SRN can be achieved by tuning the channel thickness. The proposed device can open new avenues for the fascinating applications of next-generation neuromorphic brain-like systems, such as bio-inspired electronic skins and humanoid robots.     

Nanoparticle Removal Using Laser-Induced Plasma Shock Waves

Removal of sub-100 nm particles from substrates such as wafers and photo masks is an essential requirement in semiconductor, microelectronics, and nanotechnology applications. The proposed laser-induced plasma (LIP) based approach is an effective technique for removal of sub-100 nm particles, as the minimum tolerable particle on the substrates shrinks to sub-100 nm levels with each technological node. In the current study, our progress in sub-100 nm particle removal is reviewed, and the results of the kinetic theory simulations conducted to understand the dynamics of the gas molecule-nanoparticle interactions excited by the shock front are discussed. It is shown from the simulations and experiments that particles as small as sub-100 nm can be successfully detached. To explain possible mechanisms for the nanoparticle detachment in nanoscale, the concepts of rolling resistance moment and rocking motion are utilized as novel detachment mechanisms. The pressure experiments illustrate that the peak pressure levels achieved with the LIP shock wave fields are below damage thresholds of most substrate materials. The potential of the proposed approach as a practical noncontact, dry, fast, and damage-free method for removal of sub-100 nm particles is discussed.     

Large-scale homogeneously distributed Ag-NPs with sub-10 nm gaps assembled on a two-layered honeycomb-like TiO(2) film as sensitive and reproducible SERS substrates

We present a surface-enhanced Raman scattering (SERS) substrate featured by large-scale homogeneously distributed Ag nanoparticles (Ag-NPs) with sub-10?nm gaps assembled on a two-layered honeycomb-like TiO(2) film. The two-layered honeycomb-like TiO(2) film was achieved by a two-step anodization of pure Ti foil, with its upper layer consisting of hexagonally arranged shallow nano-bowls of 160?nm in diameter, and the lower layer consisting of arrays of about fifty vertically aligned sub-20?nm diameter nanopores. The shallow nano-bowls in the upper layer divide the whole TiO(2) film into regularly arranged arrays of uniform hexagonal nano-cells, leading to a similar distribution pattern for the ion-sputtered Ag-NPs in each nano-cell. The lower layer with sub-20?nm diameter nanopores prevents the aggregation of the sputtered Ag-NPs, so that the Ag-NPs can get much closer with gaps in the sub-10?nm range. Therefore, large-scale high-density and quasi-ordered sub-10?nm gaps between the adjacent Ag-NPs were achieved, which ensures homogeneously distributed 'hot spots' over a large area for the SERS effect. Moreover, the honeycomb-like structure can also facilitate the capture of target analyte molecules. As expected, the SERS substrate exhibits an excellent SERS effect with high sensitivity and reproducibility. As an example, the SERS substrate was utilized to detect polychlorinated biphenyls (PCBs, a kind of persistent organic pollutants as global environmental hazard) such as 3,3',4,4'-pentachlorobiphenyl (PCB-77) with concentrations down to 10(-9)?M. Therefore the large-scale Ag-NPs with sub-10?nm gaps assembled on the two-layered honeycomb-like TiO (2) film have potentials in SERS-based rapid trace detection of PCBs.     

Nanoparticle Removal Using Laser-Induced Plasma Shock Waves

Removal of sub-100 nm particles from substrates such as wafers and photo masks is an essential requirement in semiconductor, microelectronics, and nanotechnology applications. The proposed laser-induced plasma (LIP) based approach is an effective technique for removal of sub-100 nm particles, as the minimum tolerable particle on the substrates shrinks to sub-100 nm levels with each technological node. In the current study, our progress in sub-100 nm particle removal is reviewed, and the results of the kinetic theory simulations conducted to understand the dynamics of the gas molecule-nanoparticle interactions excited by the shock front are discussed. It is shown from the simulations and experiments that particles as small as sub-100 nm can be successfully detached. To explain possible mechanisms for the nanoparticle detachment in nanoscale, the concepts of rolling resistance moment and rocking motion are utilized as novel detachment mechanisms. The pressure experiments illustrate that the peak pressure levels achieved with the LIP shock wave fields are below damage thresholds of most substrate materials. The potential of the proposed approach as a practical noncontact, dry, fast, and damage-free method for removal of sub-100 nm particles is discussed.     

Controllable Fabrication of Highly Uniform Sub-10 nm Nanoparticles from Spontaneous Confined Nanoemulsification

Sub-10 nm nanoparticles are known to exhibit extraordinary size-dependent properties for wide applications. Many approaches have been developed for synthesizing sub-10 nm inorganic nanoparticles, but the fabrication of sub-10 nm polymeric nanoparticles is still challenging. Here, a scalable, spontaneous confined nanoemulsification strategy that produces uniform sub-10 nm nanodroplets for template synthesis of sub-10 nm polymeric nanoparticles is proposed. This strategy introduces a high-concentration interfacial reaction to create overpopulated surfactants that are insoluble at the droplet surface. These overpopulated surfactants act as barriers, resulting in highly accumulated surfactants inside the droplet via a confined reaction. These surfactants exhibit significantly changed packing geometry, solubility, and interfacial activity to enhance the molecular-level impact on interfacial instability for creating sub-10 nm nanoemulsions via self-burst nanoemulsification. Using the nanodroplets as templates, the fabrication of uniform sub-10 nm polymeric nanoparticles, as small as 3.5 nm, made from biocompatible polymers and capable of efficient drug encapsulation is demonstrated. This work opens up brand-new opportunities to easily create sub-10 nm nanoemulsions and advanced ultrasmall functional nanoparticles.