Plasma etching of high-k and metal gate materials

Etching characteristics of high-k dielectric materials (HfO₂) and metal electrode materials (Pt, TaN) have been studied in high-density chlorine-containing plasmas at pressures around 10 mTorr. The etching of HfO₂ was performed in BCl₃ without rf biasing, giving an etch rate of about 5 nm/min with a high selectivity of >10 over Si and SiO₂. The etching of Pt and TaN was performed in Ar/O₂ with high rf biasing and in Ar/Cl₂ with low rf biasing, respectively, giving a Pt etch rate of about several tens nm/min and a TaN etch rate of about 200 nm/min with a high selectivity of >8 over HfO₂ and SiO₂. The etched profiles were outwardly tapered for Pt, owing to the redeposition of etch or sputter products on feature sidewalls, while the TaN profiles were almost anisotropic, probably owing to the ion-enhanced etching that occurred.     

Interface reactions at TiN/HfSiON gate stacks: Dependence on the electrode structure and deposition method

We systematically investigated intrinsic and extrinsic thermal reactions at TiN/HfSiON gate stacks. The formation of an ultrathin TiO₂ interlayer was found to be an intrinsic reaction at the metal/insulator interface, but growth of SiO₂ underlayers between HfSiON and Si substrates, which determines the electrical thickness of metal-oxide-semiconductor (MOS) devices, depends on the structure and deposition method of the gate electrodes. Physical vapor deposition (PVD) grown TiN electrodes covered with W overlayers exhibited excellent thermal stability at up to 1000 °C. Formation of ultrathin TiO₂ interlayers reduced gate leakage current (I_g), and growth of the oxide underlayer was suppressed by less than a few angstroms even for 1000 °C annealing. In contrast, we found that halogen impurities within CVD-grown metal electrodes enhance interface SiO₂ growth, resulting in deterioration of equivalent oxide thickness (EOT) versus I_g characteristics of the gate stacks.