Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N₂, NH₃, NO and N₂O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO_x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N₂ anneal, the wet NH₃, NO and N₂O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO_xN_y interlayer. Among the eight anneals, the wet N₂ anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 × 10¹¹ eV^− 1 cm^− 2 and gate leakage current of 2.7 × 10^− 4 A/cm² at V_g = 1 V.     

Analysis of the energy distribution of interface traps related to tunnel oxide degradation using charge pumping techniques for 3D NAND flash applications

The energy distribution and density of interface traps (D_it) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP) technique, in view of application in a 3-demension stackable NAND flash memory cell. After P/E cycling in bulk-type devices, the interface trap density gradually increased from 1.55 × 10¹² cm⁻² eV⁻¹ to 3.66 × 10¹³ cm⁻² eV⁻¹ due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for D_it of the TFT-type cells was similar to those of bulk-type cells.     

Electrical properties of Ge metal-oxide-semiconductor capacitors with La2O3 gate dielectric annealed in different ambient

Ge metal-oxide-semiconductor capacitors with La₂O₃ as gate dielectric are fabricated by e-beam evaporation of La₂O₃ followed by post-deposition annealing in different gases (NH₃, N₂, NO, N₂O and O₂). Experimental results indicate that the NH₃, NO, N₂O and O₂ anneals give higher interface-state and oxide-charge densities, and thus larger gate leakage current, with the highest for the O₂ anneal due to the growth of an unstable GeO_x interlayer. On the other hand, the NH₃ annealing improves the k value of the dielectric, while the annealings in O₂-containing ambients (NO, N₂O and O₂) lead to the formation of a low-k GeO_x interlayer, thus decreasing the equivalent k value. Compared with the above four samples, the sample annealed in N₂ exhibits not only larger k value (18.3) and smaller capacitance equivalent thickness (2.14 nm), but also lower leakage current density (~ 10⁻³ Acm^− 2 at V_g = 1 V) and smaller interface-state density (4.5 × 10¹¹ eV^− 1 cm^− 2).     

Structural and electrical properties of HfO2/Dy2O3 gate stacks on Ge substrates

In the present work we report on the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with HfO₂/Dy₂O₃ gate stack dielectrics, deposited by molecular beam deposition on p-type germanium (Ge) substrates. Structural characterization by means of high-resolution Transmission Electron Microscopy (TEM) and X-ray diffraction measurements demonstrate the nanocrystalline nature of the films. Moreover, the interpretation of the X-ray reflectivity measurements reveals the spontaneous growth of an ultrathin germanium oxide interfacial layer which was also confirmed by TEM. Subsequent electrical characterization measurements on Pt/HfO₂/Dy₂O₃/p-Ge MOS diodes show that a combination of a thin Dy₂O₃ buffer layer with a thicker HfO₂ on top can give very good results, such as equivalent oxide thickness values as low as 1.9 nm, low density of interfacial defects (2-5 × 10¹² eV^− 1 cm^− 2) and leakage currents with typical current density values around 15 nA/cm² at V_g = V_FB − 1V.     

Source/drain junction fabrication for Ge metal-oxide-semiconductor field-effect transistors

We established fabrication methods for high-quality Ge n⁺/p and p⁺/n junctions using thermal diffusion of P and implantation of B, respectively. The carrier concentrations in n⁺ and p⁺ layers were as high as 4 × 10¹⁹ and 2 × 10¹⁹ cm^− 3, respectively. It was found that a peripheral surface-state current dominates the reverse leakage current in an n⁺/p junction diode. The protection of junction surfaces from plasma damage during the SiO₂ deposition was essential to achieve high-quality source/drain junctions. The surface passivation with a GeO₂ interlayer was harmful to an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) because of an increase in a surface leakage current due to inversion carriers. For a p-channel MOSFET, on the other hand, the GeO₂ interlayer plays a role in decreasing the surface leakage current.     

Photovoltaic and interface state density properties of the Au/n-GaAs Schottky barrier solar cell

The electrical and photovoltaic properties of the Au/n-GaAs Schottky barrier diode have been investigated. From the current-voltage characteristics, the electrical parameters such as, ideality factor and barrier height of the Au/n-GaAs diode were obtained to be 1.95 and 0.86 eV, respectively. The interface state distribution profile of the diode as a function of the bias voltage was extracted from the capacitance-voltage measurements. The interface state density D_it of the diode was found to vary from 3.0 × 10¹¹ eV⁻¹ cm⁻² at 0 V to 4.26 × 10¹⁰ eV⁻¹cm⁻² at 0.5 V. The diode shows a non-ideal current-voltage behavior with the ideality factor higher than unity due to the interfacial insulator layer and interface states. The diode under light illumination exhibits a good photovoltaic behavior. This behavior was explained in terms of minority carrier injection phenomenon. The photovoltaic parameters, such as open circuit voltage and short circuit current density were obtained to be 362 mV and J_sc = 28.3 μA/cm² under AM1, respectively.     

Lattice thermal expansion studies of V2GeO4F2: A topaz type oxide-fluoride

A new compound V₂GeO₄F₂ was earlier found to exist in the V₂O₃-VF₃-GeO₂ system and the structure elucidation revealed it to be iso-structural to the mineral topaz. Herein, we report the lattice thermal expansion data of this compound. The lattice thermal expansion of V₂GeO₄F₂ was studied in the temperature range of 298-873 K under a flowing helium atmosphere by the high temperature XRD (HTXRD). The coefficients of axial thermal expansions of V₂GeO₄F₂ were found to be as: α_a = 3.5 × 10⁻⁶, α_b = 6.1 × 10⁻⁶ and α_c = 7.6 × 10⁻⁶ K⁻¹. The coefficient of volume (α_V) thermal expansion was 17.3 × 10⁻⁶ K⁻¹, which is relatively low compared to many analogues silicates.     

Green luminescence from Mn ions in ZnO-GeO2 glasses prepared by sol-gel method and their glass ceramics

Zn₂SiO₄:Mn²⁺ is one of the green light luminants used for cathode ray tubes of televisions. Recently, optical materials emitting strong visible light under lower energy excitation have been expected. To obtain new luminants of high quality, we prepared Mn ion doped ZnO-GeO₂ glasses and glass ceramics from solutions of (CH₃COO)₂Zn·2H₂O, Ge(OC₂H₅)₄, and Mn(NO₃)₂·6H₂O by a sol-gel method and the subsequent heat treatment up to 1000 °C, respectively. Materials of the system xMnO-yZnO-(100 − y)GeO₂ (x = 0-5, y = 0-40) were obtained and their luminescence, excitation, and X-band electron spin resonance (ESR) spectra as well as X-ray diffraction (XRD) patterns were measured. Under UV irradiation of 254 or 365 nm, the glass ceramics showed green luminescence at 535 nm, which may be due to the ⁴T₁→⁶A₁ transition of Mn²⁺ ions incorporated in Zn₂GeO₄ polycrystals. The intensity of this green luminescence increased and the crystallinity of Zn₂GeO₄ became high with increasing the heat-treatment temperature up to 1000 °C. In materials with low crystallinity and large amount of MnO, we observed a broad, featureless ESR signal of g = 2.01. On the other hand, in a high-crystallinity and low MnO content sample heat-treated at 1000 °C, 0.1 MnO-40 ZnO-60 GeO₂, many ESR signals were found in the range of about 20-500 mT; typical signals having six hyperfine lines were at g = 2.01 (A = 8.3-8.7 mT) and g = 4.27 (A = 8.2-8.3 mT).     

Nickel diffusion in polycrystalline CuInSe2 thin films with a <112> fiber texture

Nickel diffusion in CuInSe₂ thin films was studied in the temperature range 430-520 °C. Thin films of copper indium diselenide (CuInSe₂) were prepared by selenization of CuInSe₂-Cu-In multilayered structure on glass substrate. A thin film of Nickel was deposited and annealed at different temperatures. Surface morphologies of the Ni diffused and undiffused CuInSe2 films were investigated using scanning electron microscope. The alteration of Nickel concentration in the CuInSe₂ thin film was measured by Energy Dispersive X-Ray Fluorescence (EDXRF) technique. These measurements were fitted to a complementary error function solution and the diffusion coefficients at four different temperatures were evaluated. The diffusion coefficients of Ni in CuInSe₂ films were estimated from concentration profiles at temperatures 430-520 °C as D = 1.86 × 10^− 7(cm²s^− 1)exp[− 0.68(eV)/kT].     

High frequency characteristics of tin oxide thin films on Si

High frequency characteristics of tin oxide (SnO₂) thin films were studied. SnO₂ thin films have been successfully grown on n-type Si (111) substrates by using a spray deposition technique. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the metal-oxide-semiconductor (Au/SnO₂/n-Si) Schottky diodes were investigated in the high frequency range from 300 kHz to 5 MHz. It has been shown that the interface state density, D_it, ranges from 2.44 × 10¹³ cm⁻² eV⁻¹ at 300 kHz to 0.57 × 10¹³ cm⁻² eV⁻¹ at 5 MHz and exponentially decreases with increasing frequency. The C-V and G/ω-V characteristics confirm that the interface state density and series resistance of the diode are important parameters that strongly influence the electrical parameters exhibited by the metal-oxide-semiconductor structure.     

A study on the interface and bulk charge density of AlN films with sputtering pressure

An attempt to correlate deposition-induced effects and the morphological properties with the electrical properties of the aluminum nitride (AlN) films have been made. The AlN film was sputter deposited on silicon while increasing the pressure in steps from 2×10⁻³ to 8×10⁻³ mbar. An X-ray diffractogram revealed that the intensity of (0 0 2) orientation increased till 6×10⁻³ mbar pressure, but it changed to (1 0 0) orientation of the AlN film at 8×10⁻³ mbar. The FTIR spectra of the absorption band of the films were observed around 682 cm⁻¹ and became prominent at 6×10⁻³ mbar. A decrease in the grain size was seen by SEM images at 8×10⁻³ mbar. The AFM measurements revealed that the surface roughness varied from 1.56 to 3.24 nm with pressure. It was found that the insulator charge density (Q_in) increased from 1.4×10¹¹ cm⁻² to 1.3×10¹² cm⁻² with increase in pressure. On the other hand, the interface state density (D_it) was found minimum (7.3×10¹¹ eV⁻¹ cm⁻²) at 6×10⁻³ mbar. It is found that presence of the Q_in and D_it are primarily governed by the sputtering pressure of the AlN film.     

The determination of interface state energy distribution of the H-terminated Zn/p-type Si Schottky diodes with high series resistance by the admittance spectroscopy

Analysis of Zn/p-Si Schottky diodes (SDs) with high resistivity has been given by admittance spectroscopy. The importance of the series resistance in the determination of energy distribution of interface states and especially their relaxation time in the SDs with high resistivity has been considered. The effect of the series resistance on capacitance-conductance/frequency characteristics has been given by comparing experimental data with theoretical data. The interface state density N_ss from the admittance spectroscopy ranges from 1.0×10¹² cm⁻² eV⁻¹ in 0.720-E_v eV to 2.03×10¹² cm⁻² eV⁻¹ in 0.420-E_v eV. Furthermore, the relaxation time ranges from 4.20×10⁻⁵ s in (0.420-E_v) eV to 3.20×10⁻⁴ s in (0.720-E_v) eV. It has been seen that the interface state density has a very small distribution range (1.0-2.03×10¹² cm⁻² eV⁻¹) that is ascribed to the predominant termination with hydrogen of the silicon surface after HF treatment.     

Further work function and interface quality improvement on Al2O3 capped high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors by incorporation of fluorine

The impact of fluorine (F) incorporation into TiN/HfO₂/SiO₂ on work function has been investigated. By process scheme optimization, F implanted through sacrificial oxide layer reveals sufficient the flat-band voltage (V_FB) shift ~ 170 mV without an equivalent oxide thickness (EOT) penalty. On the contrary, apparent EOT increasing was observed if F implanted directly through Si. Moreover, F incorporation into TiN/Al₂O₃/HfO₂/SiO₂, the V_FB shift can be up to about 250 mV or 410 mV at 10 keV with a dose of 2 × 10¹⁵ cm^− 2 or 5 × 10¹⁵ cm^− 2, respectively. Effective work function has been boosted to 4.95 eV closer to the valence band edge. Besides, interface defect density also can be improved ~ 20% by F incorporation from charge pumping result.     

Si1 − xGex metal-oxide-semiconductor capacitors with HfTaOx gate dielectrics

Interfacial reactions and electrical properties of RF sputter deposited HfTaO_x high-k gate dielectric films on Si_1 − xGe_x (x = 19%) are investigated. X-ray photoelectron spectroscopic analyses indicate an interfacial layer containing GeO_x, Hf silicate, SiO_x (layer of Hf-Si-Ge-O) formation during deposition of HfTaO_x. No evidence of Ta-silicate or Ta incorporation was found at the interface. The crystallization temperature of HfTaO_x film is found to increase significantly after annealing beyond 500 °C (for 5 min) along with the incorporation of Ta. HfTaO_x films (with 18% Ta) remain amorphous up to about 500 °C anneal. Electrical characterization of post deposition annealed (in oxygen at 600 °C) samples showed; capacitance equivalent thickness of ~ 4.3-5.7 nm, hysteresis of 0.5-0.8 V, and interface state density = 1.2-3.8 × 10¹² cm^− 2 eV^− 1. The valence and conduction band offsets were determined from X-ray photoelectron spectroscopy spectra after careful analyses of the experimental data and removal of binding energy shift induced by differential charging phenomena occurring during X-ray photoelectron spectroscopic measurements. The valence and conduction band offsets were found to be 2.45 ± 0.05 and 2.31 ± 0.05 eV, respectively, and a band gap of 5.8 ± 05 eV was found for annealed samples.     

Thermal stability of advanced gate stacks consisting of a Ru electrode and Hf-based gate dielectrics for CMOS technology

Metallic Ru and Hf-based dielectrics such as HfO₂, HfSiO_x and HfSiON, are promising materials for the gate electrode and gate dielectrics, respectively. This paper reports on the thermal stability of gate stack systems comprised of Ru/Hf-based dielectrics. Layers of both types of material were prepared on Si substrate by metal-organic chemical vapour deposition (MOCVD). The stacks underwent exposure by rapid thermal annealing (RTA) in pure nitrogen ambience at temperatures 800, 900, and 1000 °C for 10 s. The samples were analysed using Rutherford backscattering spectrometry (RBS). Small changes were found in the stacks treated at 800 and 900 °C. The most stable stack was found to be one with a HfSiON dielectric layer, which was resistant also at temperature 900 °C. However, the annealing at 1000 °C induced massive diffusion at both interfaces for all types of stack. The results imply a limited thermal stability of the Ru/Hf-based dielectric gate stacks during the source/drain activation step.     

IR spectra and dielectric properties of Cu–Ge ferrite

The mixed ferrite Cu_1+xGe_xFe_2−2xO₄; where x = 0.0, 0.05, 0.1, 0.15, 0.2, 0.25 and 0.3; was prepared from high purity oxides using the standard ceramic technique. The IR spectra were recorded on the range from 200 to 1000 cm⁻¹. The two primary bands corresponding to tetrahedral ν_A and octahedral ν_B were observed around 575 cm⁻¹ and 400 cm⁻¹, respectively. It was found the threshold frequency ν_th for the electronic transition increases with increasing the Ge content. The Debye's temperature θ_D was calculated and it was found dependent on the type of charge carriers. AC conductivity σ_ac with dielectric properties (dielectric constant ?′, dielectric loss ?″ and loss tangent tan δ) as a function of frequency (f = 10² → 10⁶ Hz) at room temperature have been measured. The dispersion of the dielectric properties was discussed in the light of Koop's phenomenological theory.     

Order-disorder phase transitions and high-temperature oxide ion conductivity of Er2+xTi2−xO7−δ (x = 0, 0.096)

The Er_2+xTi_2−xO_7−δ (x = 0.096; 35.5 mol% Er₂O₃) solid solution and the stoichiometric pyrochlore-structured compound Er₂Ti₂O₇ (x = 0; 33.3 mol% Er₂O₃) are characterized by X-ray diffraction (phase analysis and Rietveld method), thermal analysis and optical spectroscopy. Both oxides were synthesized by thermal sintering of co-precipitated powders. The synthesis study was performed in the temperature range 650-1690 °C. The amorphous phase exists below 700 °C. The crystallization of the ordered pyrochlore phase (P) in the range 800-1000 °C is accompanied by oxygen release. The ordered pyrochlore phase (P) exists in the range 1000−1200 °C. Heat-treatment at T ≥ 1600 °C leads to the formation of an oxide ion-conducting phase with a distorted pyrochlore structure (P2) and an ionic conductivity of about 10⁻³ S/cm at 740 °C. Complex impedance spectra are used to separately assess the bulk and grain-boundary conductivity of the samples. At 700 °C and oxygen pressures above 10⁻¹⁰ Pa, the Er_2+xTi_2−xO_7−δ (x = 0, 0.096) samples are purely ionic conductors.     

Comparison of Ohmic contact resistances of n- and p-type Ge source/drain and their impact on transport characteristics of Ge metal oxide semiconductor field effect transistors

We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal-oxide-semiconductor field-effect transistor). The poor electron transport property is primarily attributed to the low dopant activation efficiency and high contact resistance. Results are supported by analyzing source/drain Ohmic metal contacts to n-type Ge using the transmission line method. Ni contacts to Ge nMOSFETs exhibit specific contact resistances of 10^− 3-10^− 5 Ω cm², which is significantly higher than the 10^− 7-10^− 8 Ω cm² of Ni contacts to Ge pMOSFETs. The high resistance of Ni Ohmic contacts to n-type Ge is attributed mainly to insufficient dopant activation in Ge (or high sheet resistance) and a high tunneling barrier. Results obtained in this work identify one of the root causes of the lower than expected Ge nMOSFET transport issue, advancing high mobility Ge channel technology.     

Synthesis of (1 − x)Ca2/5Sm2/5TiO3-xLi1/2Nd1/2TiO3 ceramic powder via ethylenediaminetetraacetic acid precursor

(1 − x)Ca_2/5Sm_2/5TiO₃-xLi_1/2Nd_1/2TiO₃ (CSLNT) ceramic powder was prepared by a liquid mixing method using ethylenediaminetetraacetic acid (EDTA) as the chelating agent. TG, DTA, XRD and TEM characterized the precursors and derived oxide powders. When x = 0.3, perovskite CSLNT was synthesized at 1000 °C for 3 h in air. The CSLNT (x = 0.3) ceramics sintered at 1200 °C for 3 h show excellent microwave dielectric properties of ?_r = 99, Q_f = 6200 GHz and τ_f = 9 × 10⁻⁶ °C⁻¹.     

Deposition and post-deposition annealing of thin Y2O3 film on n-type Si in argon ambient

Thin (∼5.0 nm) Y₂O₃ films were deposited on n-type Si (1 0 0) substrate using RF magnetron sputtering. Detailed studies on the effects of post-deposition annealing (PDA) temperatures (400, 600, 800, and 1000 °C) in argon ambient on these films were performed by X-ray diffraction (XRD), Fourier transform infrared spectrometer (FTIR), field emission scanning electron microscopy, and atomic force microscopy. Interfacial layer (IL) of SiO₂ in between Y₂O₃ and the Si substrate for sample annealed from 400 to 800 °C had been suggested from the results of FTIR. As for sample annealed at 1000 °C, presence of IL might consist of both Y₂Si₂O₇ and/or SiO₂ through the detection of Y₂Si₂O₇ compound and Si–O chemical bonding from XRD and FTIR analysis, respectively. For as-deposited sample, no detectable chemical functional group at the IL was recorded. Electrical characteristics of the Y₂O₃ films were acquired by fabricating metal-oxide–semiconductor capacitor as test structure. An improvement in the breakdown voltage (V_B) and leakage current density (J) was perceived as the PDA temperature increased. Of the PDA samples, the attainment of the lowest effective oxide charge, interface trap density, total interface trap density, and the highest barrier height at 1000 °C had contributed to the acquisition of the highest V_B and lowest J.