Design for ASIC reliability for low-temperature applications

A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges.     

Emerging SiGe HBT reliability issues for mixed-signal circuit applications

We review the emerging reliability issues associated with high-performance SiGe HBT technologies which are being increasingly deployed in a wide variety of mixed-signal circuit applications. For the purposes of this work, we define the concept of device "reliability" to be broader than its standard usage in the industry, to include all possible transistor degradation mechanisms, for all possible mixed-signal circuit designs, in any of the various intended mixed-signal applications. For instance, in addition to classical device reliability mechanisms associated with reverse emitter-base and high forward current density stress, new reliability issues for SiGe HBTs, including impact-ionization induced "mixed-mode" stress, scaling-induced breakdown voltage compression and operating point instabilities, geometrical scaling-induced low-frequency noise variations, and the impact of ionizing radiation on device and circuit reliability, are also addressed.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

A novel process variation immune dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z$$^{}$$FET) based on transition metals

Transition metal (TM) electrodes based dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z\(^{2}\)FET) is reported in this paper. The work-function engineering of TM electrodes is used for charge plasma based electrostatic pseudo doping. Work-function difference between TM electrodes and the undoped silicon film induces p\(^{+}\) and n\(^{+}\) regions in the film. TMs exhibit easy tunability of work-function and their CMOS fabrication compatibility pledges for their potential applications as these electrodes. A technology computer-aided design simulation study is performed to provide physical insight into its working mechanism and performance. It exhibits all the inherent characteristics of conventional Z\(^{2}\)FET, viz. zero slope switching, high \(I_{ON}/I_{OFF}\) ratio, lower operating voltages, immunity towards hot electron degradation and gate controlled hysteresis. The detrimental doping control issues, mobility degradation due to heavy doping and statistical random dopant fluctuations can no more obviate the device performance, it results in more process variations immune design. Hence it can be a potential fast switching transistor.     

Analysis of the floating‐gate transistor using the charge sheet model

The multiple‐input floating‐gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple‐input floating‐gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple‐input floating‐gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.     

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson’s equation using “variable separation technique”. The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.     

Experimental verification of the physics and structure of thebipolar junction transistor

The authors present an electrical characterization of discrete bipolar junction transistor (BJT) devices, with nonuniform doped emitter and base zones. The measurement of the I-V and C-V characteristics of the emitter-base and the collector-base junctions and the common emitter current gain allows to determine relevant parameters of the device. These are the built-in voltage of both junctions, the impurity gradient profiles, the electrical area of both junctions, the base and the emitter Gummel numbers and the collector doping. The whole experiment can be conducted in a laboratory session of 3-4 hour length and it is specifically addressed to students taking lectures in semiconductor device physics. The results obtained give a deep insight into both the physical structure and the physical processes involved in the transistor behavior     

一种复合终端逆阻IGBT数值仿真分析

绝缘栅双极型晶体管(insulated gate bipolar transistor,IGBT)本身不具有反向阻断能力,因此在电路中通常与二极管组合使用。为降低使用成本,减小寄生电感,续流二极管与IGBT通过工艺集成在同一芯片上,由此提出了具有反向阻断能力的逆阻型IGBT。针对常规逆阻IGBT终端面积大的问题,提出了一种改进型复合终端结构,采用双掺杂场限环,在P型场限环旁边引入N型轻掺杂区。改进结构减小了耗尽区横向扩展速率,增强器件可靠性,节省终端面积占用并提高了终端效率。     

Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit

In this paper a methodology for performing electrothermal analyses on integrated circuits is introduced. Using the relaxation method, standard electrical and thermal simulators, which are often used in the design process, are coupled through an efficient interface program. The simulator is capable of performing steady-state and transient analysis at device and chip levels. A variable-time-step technique has been implemented to reduce the computational time for a given set of computational resources. The simulator has been validated on different structures such as the bipolar junction transistor to predict the temperature distribution and the device performance in an amplifier circuit and an integrated current-mirror circuit. The simulation results are compared to experimental results to verify the performance of the electrothermal simulator and the accuracy of the thermal model. Simulation results demonstrate that the approach is suitable to model the thermal effects of integrated circuits in a more time-efficient, accurate and user-friendly fashion.     

Improved description of base dynamics in the modelling of bipolar transistors

An improved non-linear high-frequency model for the bipolar transistor is presented, based on considerations of the dynamics of the charge stored in the base region. the model incorporates higher-order circuit elements in order to obtain increased accuracy in circuit simulation at high frequencies. the model is derived from device physics by solving the diffusion equation in the base region by means of a quasi-static expansion. the result is a more accurate circuit representation, which can be added to existing bipolar transistor models. Simulation examples are given and the possible convergence problems associated with the model are discussed.     

A simulation-based evolutionary technique for inverse doping profile problem of sub-65 nm CMOS devices

In this paper, we utilize an evolutionary technique for inverse doping profile problems of the 65 nm complementary metal oxide semiconductor (CMOS) devices. The approach mainly bases upon the process simulation, device simulation, evolutionary strategy, and empirical knowledge. For a set of given measured I-V curves of the 65 nm CMOS, a developed prototype performs the optimization task to automatically calibrate and inversely search out, for example the doping recipe and device physical model parameters. The simulation-optimization-coupled methodology is complicated theoretically, but our preliminary results imply that it may benefit the development of fabrication technology and can be used for the performance diagnosis, in particular, for sub-65 nm devices.     

A three-terminal piecewise-linear modelling approach to dc analysis of transistor circuits

The simulation of electronic circuits by computer has become an important part of present-day circuit analysis and design, especially in the area of integrated circuit design. One of the goals in computer simulation of integrated circuits is to have a program ‘package’ for which the input consists of chip fabrication data (mask dimensions, impurity profiles, material data such as carrier lifetimes) and the output displays the complete circuit response. This requires both an efficient modelling approach and a fast circuit analysis method. In this paper a simulation method is described which generates dc responses (in the form of operating points or transfer characteristics) of transistor circuits directly from physical parameter data. The basis of the method is a two-dimensional piecewise-linear approach to the dc modelling of bipolar transistors. The model is directly used in a piecewise-linear circuit analysis program to simulate the dc response of a given circuit.     

DESIGNING OPTIMUM SNUBBER CIRCUITS OR THE TRANSISTOR BRIDGE CONFIGURATION

ABSTRACT

Snubbers are used in power transistor switching circuits to keep the device operation within its Safe Operating Area (SOA) during switching. The conventional series and shunt snubbers are satis -factory in a single transistor circuit. However, these are not satisfactory for a totem pole transistor arrangement. In this paper various snubber circuits are analysed and their effects are discussed. A snubber circuit is developed and tested which is suitable for transistors in bridge configuration. The circuit is thoroughly analysed and design equations are derived for the snubber components.     

Equivalent circuit for RF flexural free-free MEMS resonators

A method to extract a lumped-parameter equivalent circuit for a free-free flexural MEMS resonator, based on the Euler-Bernoulli beam equation and exploiting a modal analysis approach, is presented. The dynamic behaviour predicted by the equivalent circuit is compared with FEM simulations, and the effect of a geometrical mismatch is investigated as well. The resonance frequency and the quality factor are correctly predicted. The method could be used for more complex systems of interconnected beams. The circuit can be used as a quick and intuitive analysis tool for the system-level designer and to allow the simulation of the device in a system-level design environment.     

PastA—the characterization of the inherent fluctuations in the fabrication process for circuit simulation

For worst-case analysis, Monte Carlo analysis, yield optimization and design centring, the variations and correlations of the device model parameters in the electrical circuit simulation are of fundamental significance. This paper describes a method for the complete characterization of the inherent fluctuations in the fabrication process for the simulation in IC design. the emphasis is placed on analogue simulation owing to the complex connections between circuit design and technology and the multitude of devices with correlated parameters; nevertheless, statistical requirements for digital simulation can be fully covered. This characterization works with all technologies whether CMOS, BiCMOS or bipolar. the prerequisites are accurate nominal device model parameters for the circuit simulation and information about fabrication statistics, e.g. process control monitor measurements. A new approach with connection coefficients for the calculation of the correlation coefficients is presented. Dependent parameters can be easily defined through a connection hierarchy. With the presented approach the variations and correlations of model parameters for simulation can be generated from estimates or measurements of the fabrication process. Based on sensitivity analysis, the variations and correlations of design objectives can be estimated. This enables the designer to do circuit analysis and optimization (limit parameters, worst-case distances) as well as Monte Carlo analysis.     

旋转双断点塑壳断路器机构的动态仿真与优化

应用虚拟样机技术商业软件ADAMS创建了旋转式双断点塑壳断路器操作机构的动力学模型,并进行了动态仿真.在此基础上,研究了弹簧刚度系数、连杆的相对位置、杆件的质量等因素对分断速度的影响.以操作机构的关键轴的位置为设计变量,进行了机构的优化设计,为国内开发新一代低压塑壳断路器提供参考.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

Investigation of fault modes of voltage-fed inverter system forinduction motor drive

The reliability of power electronics systems is of paramount importance in industrial, commercial, aerospace, and military applications. The knowledge about the fault mode behavior of a converter system is extremely important from the standpoint of improved system design, protection, and fault tolerant control. This paper describes a systematic investigation into the various fault modes of a voltage-fed PWM inverter system for induction motor drives. After identifying all the fault modes, a preliminary mathematical analysis has been made for the key fault types, namely, input supply single line to ground fault, rectifier diode short circuit, inverter transistor base drive open, and inverter transistor short-circuit conditions. The predicted fault performances are then substantiated by simulation study. The study has been used to determine stresses in power circuit components and to evaluate satisfactory post-fault steady-state operating regions. The results are equally useful for better protection system design and easy fault diagnosis. They will be used to improve system reliability by using fault tolerant control     

Impact of series resistance on Si nanowire MOSFET performance

In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by dividing it into five resistance components namely spreading resistance, extension resistance, interface resistance, deep source-drain resistance and contact resistance. The model is validated using 3-D device simulations of 22 nm GAA devices with Source/Drain extension (SDE) length of 15 nm to 35 nm, diameter of 8 nm to 16 nm and oxide thickness of 10 A to 40 A for both n-FET and p-FET. It is found that the spreading resistance due to lateral doping gradient contributes significantly to the total series resistance. Further, the dependence of NW device performance on series resistance is quantitatively investigated with change of diameter, SDE length and Source/Drain (S/D) implantation dose. Results show a strong NW device performance dependence on S/D doping profile and extension length defining a design trade-off between Short Channel Effects (SCEs) and series resistance. It is seen that the increase in series resistance due to increase of extension length or decrease of implantation dose beyond a certain limit reduces the device drive current significantly with nearly constant OFF-state leakage current. Hence, optimization of extension length and S/D implant dose is an important device design issue for sub 22 nm technology nodes.