功率半导体器件的场限环研究

分析了场限环结构原理,总结了影响击穿电压的相关因素.采用圆柱坐标对称解进行分析,讨论了给定击穿电压情殚况下场限环结构的电场分布和峰值电场表达式及各种确定场限环个数的方法的.最后用流行的2-D半导体器件模拟工具MEDICI对器件终端进行相关模拟,尤其是表面电荷对带场限环的击穿电压和优化环间距的影响做了大量的分析模拟.得出的结论与文献中的数值模拟结果相符合,对设计优化场限环有一定的指导性.     

沟槽负斜角终端结构的耐压机理与击穿特性分析

对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法.基于GTR台面终端结构,在功率MOSFET中引入了一种类似的沟槽负斜角终端结构.利用1SE软件对其耐压机理和击穿特性进行了模拟与分析.结果表明,采用沟槽负斜角终端结构会使功率MOSFET的耐压达到其平行平面结击穿电压的92...     

高压VDMOSFET击穿电压优化设计

通过理论计算,优化了外延层厚度和掺杂浓度,对影响击穿电压的相关结构参数进行设计,探讨了VDMOSFET的终端结构。讨论了场限环和结终端扩展技术,提出了终端多区设计思路,提高了新型结构VDMOSFET的漏源击穿电压。设计了800V、6A功率VDMOSFET,同场限环技术相比,优化的结终端扩展技术,节省芯片面积10.6%,而不增加工艺流程,漏源击穿电压高达882V,提高了3%,由于芯片面积的缩小,平均芯片中测合格率提高5%,达到了预期目的,具有很好的经济价值。     

一种沟槽-场限环复合终端结构的设计

为了改善硅功率器件击穿电压性能以及改善IGBT电流的流动方向,提出了一种沟槽-场限环复合终端结构。分别在主结处引入浮空多晶硅沟槽,在场限环的左侧引入带介质的沟槽,沟槽右侧与场限环左侧横向扩展界面刚好交接。结果表明,这一结构改善了IGBT主结电流丝分布,将一部分电流路径改为纵向流动,改变了碰撞电离路径,在提高主结电势的同时也提高器件终端结构的可靠性;带介质槽的场限环结构进一步缩短了终端长度,其横纵耗尽比为3.79,较传统设计的场限环结构横纵耗尽比减少了1.48%,硅片利用率提高,进而减小芯片面积,节约制造成本。此方法在场限环终端设计中非常有效。     

场限制环的安全环距设计原理

场限制环作为一种可与许多器件工艺相容的ＰＮ结终端得到了广泛应用。存在的一个问题是其效果随结构参数有过分敏感的变化。文中认为：作为设计指导思想的最佳环距原则是加重这一敏感性的重要原因。作为改进，提出了新的安全环距设计原则。按安全环距原则设计，除可明显缓解终端效果随结构参数敏感变化的问题外，还可有效地提高在同样结构和工艺条件下所制成器件的额定电压。     

SiC肖特基势垒二极管的反向特性

在n型4H-SiC衬底上的n型同质外延层的Si面制备了纵向肖特基势垒二极管(SBD),研究了场板、场限环及其复合结构等不同终端截止结构对于反向阻断电压与反向泄漏电流的影响。场板(FP)结构有利于提高反向阻断电压,减小反向泄漏电流。当场板长度从5μm变化到25μm,反向阻断电压随着场板长度的增加而增加。SiO2厚度对于反向阻断电压有重要的影响,当厚度为0.5μm,即大约为外延层厚度的1/20时,可以得到较大的反向阻断电压。当场限环的离子注入区域宽度从10μm变化到70μm,反向阻断电压也随之增加。FLR和FP复合结构对于改善反向阻断电压以及反向泄漏电流都有作用,同时反向阻断电压对于场板长度不再敏感。采用复合结构,在10μA反向泄漏电流下最高阻断电压达到1 300V。讨论了离子注入剂量对于反向阻断电压的影响,注入离子剂量和反向电压的关系表明SBD结构不同于传统PIN结构的要求。当采用大约为150%理想剂量的注入剂量时才可达到最高的反向阻断电压而不是其他报道的75%理想剂量,此时的注入剂量远高于PIN结构器件所需的注入剂量。     

Structure of quasi-optimal time algorithm for analog circuits design

The generalized methodology developed earlier for analog circuits design and based on applying the optimal control theory is the basis for developing an optimal or quasi-optimal design algorithm. In this context the most crucial criterion making it possible to find the required structure of algorithm is the behavior of the Lyapunov function determined for circuit optimization process. Characteristics of the Lyapunov function and its derivative form the basis of search for the optimal structure of control vector which, in turn, determines the algorithm structure. A functional block diagram of the quasi-optimal algorithm implementing the main ideas of the earlier developed methodology has been built, and the main characteristics of this algorithm were determined in comparison with the traditional approach and with quasi-optimal design strategy.     

Si基JBS整流二极管的设计与制备

基于JBS整流二极管理论,详细介绍了一种Si基JBS整流二极管设计方法、制备工艺及测试结果。在传统肖特基二极管(SBD)有源区,利用光刻和固态源扩散工艺形成掺硼的蜂窝状结构,与n型衬底形成pn结,反向偏置时抑制了因电压增加引起的金属-半导体势垒高度降低,减小了漏电流;采用离子注入形成两道场限环的终端结构,有效防止了边缘击穿,提高了反向击穿电压。对制备的器件使用Tektronix 370B可编程特性曲线图示仪进行了I-V特性测试,结果表明本文设计的Si基JBS整流二极管正向压降VF=0.78 V(正向电流IF=5 A时),反向击穿电压可达340 V。     

高压IGBT线性变窄场限环终端设计

为使3300 V及以上电压等级绝缘栅双极型晶体管(IGBT)的工作结温达到150℃以上,设计了一种具有高结终端效率、结构简单且工艺可实现的线性变窄场限环(LNFLR)终端结构。采用TCAD软件对这种终端结构的击穿电压、电场分布和击穿电流等进行了仿真,调整环宽、环间距及线性变窄的公差值等结构参数以获得最优的电场分布,重点对比了高环掺杂浓度和低环掺杂浓度两种情况下LNFLR终端的阻断特性。仿真结果表明,低环掺杂浓度的LNFLR终端具有更高的击穿电压。进一步通过折中击穿电压和终端宽度,采用LNFLR终端的3300 V IGBT器件可以实现4500 V以上的终端耐压,而终端宽度只有700μm,相对于标准的场限环场板(FLRFP)终端缩小了50%。     

3300V碳化硅肖特基二极管及混合功率模块研制

基于数值仿真结果,采用结势垒肖特基(JBS)结构和多重场限环终端结构实现了3 300 V/50 A 4H-SiC肖特基二极管(SBD),所用4H-SiC外延材料厚度为35 μm、n型掺杂浓度为2× 1015cm-3.二极管芯片面积为49 mm2,正向电压2.2V下电流达到50 A,比导通电阻13.7 mΩ· cm2;反偏条件下器件的雪崩击穿电压为4 600 V.基于这种3 300 V/50 A 4H-SiC肖特基二极管,研制出3 300 V/600 A混合功率模块,该模块包含24只3 300 V/50 A Si IGBT与12只3 300 V/50 A 4H-SiC肖特基二极管,SiC肖特基二极管为模块的续流二极管.模块的动态测试结果为:反向恢复峰值电流为33.75 A,反向恢复电荷为0.807 μC,反向恢复时间为41 ns.与传统的Si基IGBT模块相比,该混合功率模块显著降低了器件开关过程中的能量损耗.     

Design and Analysis of Shock-Absorbing Structure for Flat Panel Display

In order to protect the fragile panel of a liquid crystal display (LCD) from damage caused by shock, a shock-absorbing structure designed to absorb most of the shock energy can be installed between the panel and the frame. The design methodology proposed in this paper uses the topology optimization technique in designing this shock-absorbing structure. The objective is to minimize the maximal panel stress with the shock-absorbing structure, which is designed to be of minimal weight. An algorithm which integrates three modules-the finite-element software ANSYS/LS-DYNA used as the structural analysis tool, the optimization module based on the differential evolution method, and a topology module - is developed to achieve crashworthiness design. Numerical results show that an optimal layout of the shock-absorbing structure with minimal weight is obtained. And, this shock-absorbing structure is proven to effectively increase LCD shock resistance.     

Reflection Enhanced Compensation of Lossy Traces for Best Eye-Diagram Improvement Using High-Impedance Mismatch

As the signal rates increase toward the multigigabit range, the lossy effect of typical transmission lines on the signal quality of printed circuit boards has become a more and more significant issue. This paper introduces the concept of reflection gain resulted from the high-impedance mismatch to improve the eye diagram at the receiving end by inserting the inductance or high-impedance line between the signal trace and matched termination. A systematic design methodology is also proposed here to tell how to resolve the optimal high-impedance elements for the finest compensation efficiency. Moreover, with the optimal inductance, a design formula based on the circuit theory is derived accordingly to estimate the approximate length of high-impedance line and after that, the ultimate performance of this compensation method is also evaluated. Eventually, some experiments are implemented to validate the design technique.      

Optimization and surface charge sensitivity of high-voltageblocking structures with shallow junctions

The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5×10¹¹ cm^-2 net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities     

500V VDMOS功率器件终端结构设计

本文论述了VDMOS器件的一种场板-分压环结合的终端结构。对1.5A/500V功率器件进行了分析和设计,并给出了终端电场分布的模拟结果。投片试制结果与设计预期参数相符。     

Design methodology and simulation tool for floating ring termination technique

A new methodology to optimize the design of floating ring (FR) termination technique for high voltage device is presented. The basic idea is to simulate the blocking capability of the structure with only one guard ring and then extend the results to a multiple FR system. A second advantage of our method is to include the ring width in the optimization process. The effectiveness and efficiency of our methodology is illustrated by optimizing a FR structure with a junction depth x_j=5 μm and Si substrate doping 2·10¹⁴ cm⁻³. A seven rings structure is optimized giving 85% efficiency in respect to the ideal plane parallel junction breakdown voltage V_BD=840 V. The simulation results are generated by the user-oriented simulation program POWER2D for studying the voltage handling capability of arbitrary shaped power semiconductor devices. A special algorithm is implemented ensuring very fast and automatic search of the breakdown via the ionization integrals calculus. An efficient numerical algorithm to drastically reduce the number of iterations when adjusting the quasi-Fermi potential of the floating rings has also been developped     

金属场板加SIPOS电阻场板的新型终端技术

本文介绍了一种金属场板结合SIPOS电阻场板的新型终端结构,该终端能实现平面结理想击穿值的80％以上。对这种终端结构的设计,采用了一种简单方法。根据实验结果,对金属场板和SIPOS电阻场板的互补功能进行了详细的分析。     

Analysis of the control vector structure in analog networks design

The methodology of analog networks design developed on the basis of the optimum control theory is used for determining the vector structure controlling the optimization process. The analysis of control vector structure is performed by using the Lyapunov function concept of design process. The investigation of behavior of this function and its time derivative makes it possible to determine optimal switching points of the control vector. Such an approach allows us to minimize the total processor time of network design by correcting the control vector structure in terms of the characteristics of the initial period of design. Numerical results of the optimization process of networks with arbitrary number of transistors indicate the possibility of design process control for minimization of the total processor time.     

Response Surface Based Optimization Approach for Thermal Placement Design of Chips in Multiple-Chip Modules

This paper attempts to perform thermal enhancement of planar multiple-chip modules (MCMs) containing a number of chips of equal and/or unequal power through optimal chip placement design. To achieve the goal, an effective design approach is presented for the thermal design optimization problems in the context of models of placement of chips in MCMs. The approach combines the use of the currently proposed response surface (RS) based methodology, which is an optimization algorithm and a finite element modeling technique. The proposed RS-based methodology is used for creating a macro mathematical expression of the design objective of the thermal optimization problem, i.e., the total chip junction temperature of the system, associated with the design parameters, including the chip location and power. The validity of the mathematical expressions constructed is verified through two approaches. Furthermore, to make the constructed mathematical expression more compact while maintaining the associated solution accuracy, the backward variable elimination technique is employed. The effectiveness of the proposed design optimization methodology is demonstrated through several design case studies involving planar plastic ball grid array type MCMs. It is found that the proposed RS-based methodology could accurately define the macro mathematical model of the total system chip junction temperature in terms of the chip location and power. In addition, results show that the current optimal chip placement design can provide a minimal system temperature.     

Analytic termination metrics for pin-to-pin lossy transmissionlines with nonlinear drivers

A significant percentage of the critical nets in high-performance systems are of the pin-to-pin type. To optimally design these nets such that signal integrity is preserved, efficient analytical metrics for transmission line termination are a valuable part of a system-level designer's toolset. Using the symbolic moment-based expressions in this paper, proper termination can be determined via a single-step procedure, without any preprocessing steps and/or time-domain simulations. Driver nonlinearities and effects of nonzero rise-time are also considered in the proposed termination methodology     

Simulation-based design optimization methodologies applied to CFD

Finding the optimal physical design for an electronic system is extremely time-consuming. In this paper, we describe a sequential global optimization methodology that can lead to better designs in less time, and illustrate its use by optimizing the design of a heat sink for a simple system. The results show the need for a global approach, the insights that can be gained through automated design optimization, and illustrate the efficiency of the reported methodology in finding the optimum design.