A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-/spl mu/m-long 1.2-V thin-oxide transistor with a 0.22-/spl mu/m-long 3.3-V thick-oxide transistor in a 0.13-/spl mu/m CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 /spl mu/m is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 /spl mu/m) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V/sub T/) and breakdown voltage in conventional CMOS technologies without adding any process modifications.     

Millimeter-wave voltage-controlled oscillators in 0.13-/spl mu/m CMOS technology

This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.     

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

Noise property of a quadrature balanced VCO

A quadrature balanced voltage controlled oscillator (B-VCO) with current source switching is proposed and analyzed. This letter shows analytically that the switching improves the phase noise. A switched transistor is also used as a coupling transistor to generate quadrature signals without degrading the phase noise. To investigate the effect of quadrature coupling on the phase noise, a single B-VCO and a quadrature B-VCO are implemented with identical components in an 0.18-/spl mu/m CMOS process. Both VCO cores draw about 8.8mA under a low bias voltage of 1.8V. The oscillation frequencies are 10.21GHz and 10.81GHz. The measured phase noises of the single at an offset frequency of 1MHz VCO is -114.83 dBc/Hz while that of the quadrature VCO is -116.67 dBc/Hz. The quadrature B-VCO is superior to the single B-VCO with respect to phase noise and oscillation frequency in the X-band.     

A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-/spl mu/m CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is /spl plusmn/200 /spl mu/A. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of /spl plusmn/100 /spl mu/A.     

A high-speed 64K CMOS RAM with bipolar sense amplifiers

A TTL-compatible 64K static RAM with CMOS-bipolar circuitry has been developed using a 1.2-/spl mu/m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mW active power and 100 nW standby power. A CMOS six-transistor memory cell is used. The cell size is 18/spl times/20 /spl mu/m, and the chip size is 5.95/spl times/6.84 mm. The n-p-n transistors are used in the sense amplifiers, voltage regulators, and level clamping circuits. The bipolar sense amplifiers reduce the detectable bit line swing, thus improving the worst-case bit line delay time and the sensing delay time. In order to reduce the word line delay, the MoSi layer, which has 5 /spl Omega//sheet resistivity, was used for the gate material. The n-well CMOS process is based on a scaled CMOS process, and collector-isolated n-p-n transistors and CMOS are integrated simultaneously without adding any extra process steps and without causing any degradation of CMOS characteristics. The n-p-n transistor has a 2-GHz cutoff frequency at 1 mA collector current.     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.     

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

A study of phase noise in colpitts and LC-tank CMOS oscillators

This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f/sup 2/ phase-noise region are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypes of both Colpitts and LC-tank oscillators have been implemented in a 0.35-/spl mu/m CMOS process. The best performance of the LC-tank oscillators shows a phase noise of -142dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of /spl sim/189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is /spl sim/5 dB lower.     

A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion

This paper presents a novel linearized transconductor architecture working at 1.25 V in a 0.8-/spl mu/m CMOS technology with very low power consumption. The special features of the floating-gate MOS (FGMOS) transistor are combined in weak and strong inversion leading to a simplified topology with fewer stacked transistors and a very low noise floor. The design methodology is thoroughly explained, together with the advantages and disadvantages of working with the FGMOS transistor. Furthermore, second-order effects arising from nonideal behavior of the device are analyzed and limits for the performance are established. Experimental results from a second-order low-pass/bandpass filter that was implemented using the transconductor show a tunability of over one and a half decades in the audio range, a dynamic range of over 62 dB, and a maximum power consumption of 2.5 /spl mu/W. These results demonstrate the suitability of the FGMOS transistor for implementing analog continuous-time filters, while at the same time pushing down the voltage limits of process technologies and simplifying the circuit topologies to obtain significant power savings.     

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

The collector-coupled static RAM cell

The collector-coupled static RAM cell uses a schottky collector transistor switch with merged vertical n-p-n load. The cell is constructed with two dual Schottky collector transistors and one merged dual collector n-p-n transistor. It has been fabricated in an infant oxide isolated bipolar technology and bistability has been demonstrated over four orders of magnitude in cell current (10 nA相似文献   

Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback

A transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage. The advantages of the proposed TF-VCO are described together with its detailed analysis and its cyclo-stationary characteristic. Two prototypes using the proposed TF-VCO techniques are demonstrated in a standard 0.18-/spl mu/m CMOS process. The first design using two single-ended transformers is operated at 1.4 GHz at a 0.35-V supply using PMOS transistors whose threshold voltage is around 0.52 V. The power consumption is 1.46 mW while the measured phase noise is -128.6 dBc/Hz at 1-MHz frequency offset. Using an optimum differential transformer to maximize quality factor and to minimize the chip area, the second design is operated at 3.8 GHz at a 0.5-V supply with power consumption of 570 /spl mu/W and a measured phase noise of -119 dBc/Hz at 1-MHz frequency offset. The figures of merits are comparable or better to that of other state-of-the-art VCO designs operating at much higher supply voltage.     

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

A high speed bulk CMOS C/SUP 2/L microprocessor

The CDP 1802, single-chip, 8-bit microprocessor is fabricated in C/SUP 2/L, or closed COS/MOS logic, a new structural approach to high-speed bulk silicon COS/MOS logic. In this self-aligned silicon-gate CMOS technology, the gate completely surrounds the drain providing transistor aspect ratios which maximize the transconductance to capacitance ratio and thus allow high on-chip speed. Generally, standard 6-/spl mu/m channel length C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately four times faster than standard CMOS. High density 5-/spl mu/m channel length devices further improve area and speed by factors up to 1.5. The fabrication sequence for C/SUP 2/L devices requires six photomasks (one less than standard CMOS).     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.