VLSI compressor design with applications to digital neural networks

A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. In this paper, such a compressor design based on complex complementary pass-transistor logic (C²PL) is presented. Some types of 3-2 compressors in C²PL are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressors, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct logic (CDL), our simulations show that the C²PL compressors have the best performance in power, delay and number of transistors     

Semistate theory and analog VLSI design

Semistate theory as applied to electronic circuits is reviewed in a tutorial fashion. The resulting theory is applied to the design of linear VLSI circuits using an admittance framework for which the main components are MOS capacitors, differential pairs and current mirrors. The results are extended to nonlinear designs through the use of CMOS multipliers.     

New symmetrical buffer design for VLSI applications

Novel fast buffers by the transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in their structure, therefore the design is straightforward and the well balanced speed can be easily obtained. As compared with prior work, the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer circuit shows 27% and 76% average speed enhancements on propagation delays with only 7.3% average increase in its power consumption.     

A VLSI demodulator for digital RF network applications: theory andresults

An all-digital demodulator/detector which is suitable for both analog FM and digital phase/frequency modulations is presented. The system uses complex sampling, which employs a single A/D (analog/digital) converter to sample the signal at an intermediate frequency (IF) and produce baseband in-phase (I) and quadrature phase (Q) signals, and a simplified technique for reducing the effect of the I/Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. The theory behind the demodulator/detector system is described, and an implementation using a 1.25-μm bulk CMOS VLSI process is presented. Methods are shown for extending and improving the I/Q sampling misalignment correction technique, as well as for reducing the A/D sampling rate for a given IF frequency. Simulation and experimental results illustrate system performance for both analog and digital modulations     

A computational approach to VLSI analog design

A new technique for the design of analog VLSI is described. Borrowing from digital design technology concepts, an analog processor is described which can be digitally programmed to execute a small but powerful set of analog operations. At a very high level of abstraction these instructions can be used to perform mathematical processing on analog signals directly rather than through the traditional processing chain of sampling, A/D conversion, digital processing, and D/A conversion. A key feature of the technique is the conversion of signals into logarithmic form, and the practical problems associated with this are discussed and their solutions outlined. Finally implementation of these techniques in BiCMOS, CMOS, and bipolar technologies is discussed with conclusions.     

A computational approach to VLSI analog design

A new technique for the design of analog VLSI is described. Borrowing from digital design technology concepts, an analog processor is described which can be digitally programmed to execute a small but powerful set of analog operations. At a very high level of abstraction these instructions can be used to perform mathematical processing on analog signals directly rather than through the traditional processing chain of sampling, A/D conversion, digital processing, and D/A conversion. A key feature of the technique is the conversion of signals into logarithmic form, and the practical problems associated with this are discussed and their solutions outlined. Finally implementation of these techniques in BiCMOS, CMOS, and bipolar technologies is discussed with conclusions.     

A methodology and design tools to support system-level VLSI design

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraint-driven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology     

基于VLSI设计实现的高效颜色插补算法

针对Bayer格式阵列的CMOS图像传感器(CIS)片上系统(SoC)中图像信号处理单元(ISP)的研究,提出一种适合VLSI实现的高效颜色插补算法。算法重点重建了缺失的G分量,先进行像素边缘判断,进而结合边缘方向梯度加权计算,使得G分量的重建有效避免了传统方法中易造成边缘变模糊的现象;对于B和R分量的重建,充分利用小范围内已知的像素分量值对其进行线性插补,使得插补后的值更接近真实值。通过对色彩测试标板和自然图像的模拟实验表明,该算法插补后的图像与传统算法相比更清晰、信噪比更高。算法基于VL-SI设计实现,并通过FPGA验证,结果表明,该算法易于片上实现,耗费资源892个LE,最大频率可达142MHz,完全满足实时处理需求。     

A unified discrete-time state-space model for switching converters

A unified nonlinear state-space model for arbitrary switching converters is presented, which uses discrete-time modeling of switches. Although its compact and powerful notation is valid for all types of switching circuits, perhaps its main application field is power electronics. The proposed model is valid for any electric circuit composed of ideal switches (externally or internally controlled), RLC elements and energy sources. Therefore, the model is general considering semiconductor devices as ideal switches, which are dealt with as discrete-time dynamic systems. Thus the developed model may be either a hybrid continuous-discrete-time one or a full discrete-time one. Moreover, this model is valid as a circuit simulator     

基于DVD应用的流水线RS-PC解码的VLSI设计

基于DVD数据纠错的应用，设计实现了全程流水线处理的RS-PC解码，采用分解的无逆BM(Berlekamp—Massey)算法和脉动时序控制实现RS解码器的三级流水线处理，采用行列独立的缓冲器和纠错解码器实现行列纠错的两级流水线处理。该RS-PC解码能达到非常快的处理速度，在行列纠错处理无迭代的情况下，数据率可达到每时钟一个字节。     

A unified mathematical approach to two-port calibration techniquesand some applications

A rigorous mathematical treatment of microwave network analyzer calibration and de-embedding procedures for the two-port error network representation is used in order to explain current calibration techniques in a succinct and homogeneous manner. It is demonstrated that the essence of through-delay de-embedding techniques consists in the use of two known two-port calibration standards to obtain pairs of similar matrices for the input and output error adapters. Once the characteristic vectors for these matrices are obtained, a number of different approaches can be used in order to solve for the scaling constants     

A new tungsten gate process for VLSI applications

In spite of the growing demand for MOS gates and interconnections of higher conductivity, the refractory metal gate process has not received as much attention as those using silicides because it is incompatible with the Si-gate process. The metal gate cannot withstand oxidizing annealing ambients, and source-drain formation by ion implantation is difficult because of the channeling of doping ions through the gate metal during ion implantation. In a new process developed for use in MOS VLSI fabrication, tungsten (W) is used as a gate metal because degradation of SiO2by annealing the metal/SiO2/Si structure at around 1000°C can be minimized if the metal is W. Metal oxidation is prevented by using a H2/H2O ambient for this annealing, which also allows Si to be oxidized in the same ambient. The channeling mentioned above is stopped by forming a thin layer of PSG or WOxon the W. This gate process is believed to be a step forward toward the desired compatibility.     

A VLSI design methodology for distributed arithmetic

Real-time signal processing requires fast computation of inner products. Distributed arithmetic is a method of inner product computation that uses table-lookup and addition in place of multiplication. Distributed arithmetic has previously been shown to produce novel and seemingly efficient architectures for a variety of signal processing computations; however the methods of design, analysis and comparison have been ad hoc. We propose a systematic method for synthesizing optimal VLSI architectures using distributed arithmetic.A partition of the inner product computation at the word and bit level produces a computation consisting of lookups and additions. We study two classes of algorithms to implement this computation, regular iterative algorithms and tree algorithms, each of which can be expressed in the form of a dependency graph. We use linear and nonlinear maps to assign computations to processors in space and time. Expressions are developed for the area, latency, period and arithmetic error for a particular partition and space/time map of the dependecy graph. We use these expressions to formulate a constrained optimization problem over a large class of architectures. We compare distributed arithmetic with more conventional methods for inner product computation and show how area, latency and period may be traded off while maintaining constant error.This work was supported by Ball Aerospace, Boulder, CO and by the Office of Naval Research, Electronics Branch, Arlington, VA under contract ONR 89-J-1070.     

A unified approach to IFIR filter design using B-spline functions

An efficient procedure is presented for the design of interpolated finite impulse response (IFIR) filters with linear phase. The algorithm uses the uniform B-spline function as an interpolator and solves the optimal Chebyshev approximation problem on the appropriate subinterval. The technique can be used for the design of general low-pass, high-pass and bandpass filters. Although the number of multiplications of the IFIR filter is dependent on the bandwidth and the center frequency of the desired filter, this approach nearly always provides a substantial reduction in complexity when compared to other FIR and IFIR design procedures     

An improved RC model for VLSI interconnects with applications to buffer insertion

A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from HSPICE as a bench mark, we show that among all 18 models studied, the π-configuration of AWE-RLC model yields the best accuracy. To reduce complexity subsequently computational cost without sacrificing accuracy, the AWE-RLC model is mapped to a complex RC model using moment matching. The complex RC model is further mapped to an improved RC model utilizing the principle of charge reservation. The improved RC model is employed to estimate the delay of long interconnects with buffer insertion. As compared with the conventional RC model, the improved RC model reduces the delay of interconnects with buffer insertion, the number of buffers, and the size of the buffer by 20.5, 24, and 32 %, respectively.     

A comparative study of CMOS processes for VLSI applications

A comparative study of simulated circuit performance has been made in order to determine the optimum process parameters for p-well CMOS with feature sizes of between 1 and 2 µm. it has been found that for the process considered, best speed, Power, and packing density are achieved with a substrate concentration of between 3 × 10¹⁵and 10¹⁶cm^-3and an operating voltage which is as low as possible. Higher speed can be attained at the expense of considerably more power dissipation through the use of a higher rail voltage. Silicon-on-insulator CMOS has been considered as an alternative to p-well CMOS. This technology can be expected to out-perform small geometry bulk silicon CMOS if recent improvements in material quality can be maintained.     

一种基于省时考虑的深亚微米VLSI的物理验证方法

现代VLSI开发的后端设计人员面临巨大的产品上市时间压力,尤其是对物理验证的过程而言时间更是紧张。本文结合工程经验阐述了物理验证的步骤和原理,结合Synopsys公司的物理验证工具Hercules的特点,提出了一种比较省时的物理验证流程,已用于实际数字调制芯片设计并流片。     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.