The parylene-aluminum multilayer interconnection system for wafer scale integration and wafer scale hybrid packaging

Polyimides have been considered as interlayer dielectrics for wafer scale integration (WSI) and wafer scale hybrid packaging (WSHP). However, high temperature curing steps for polyimide lead to large stresses in polyimide films. This is due to differing thermal expansion coefficients of the metal conductor, insulator and substrate materials causing yield and reliability problems. Polyimides also require the use of solvents, and tend to outgas during subsequent processing. They tend to absorb moisture with resulting degradation of dielectric constants. Also, the spin on method used to apply and planarize polyimide layers exhibits nonuniformity of thickness on large wafers. In this paper we examine parylene (Poly-p-xylylene) and some of its derivatives as possible interlayer dielectrics due to some of their attractive features. Parylene has a low dielectric constant. It can be vapor deposited at low temperatures and in vacuum. It is also highly resistant to corrosion and is a clear, transparent material with possible use for optical interconnections. This paper studies the reactive ion etching properties for polyimides and parylenes in an oxygen containing plasma under identical conditions. The etching rates of the parylenes and polyimides have been compared. The surface properties of these polymers are examined. Further, the film growth properties of aluminum deposited on the etched surfaces using the ionized cluster beam are investigated.     

MicroSMD-a wafer level chip scale package

This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability     

Loop based design for wafer scale systems

This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various topologies and reconfiguration algorithms are made within the context of percolation models     

A radix-8 wafer scale FFT processor

Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up to 4096 points with 16-bit fixed point data.     

Yield optimization in wafer scale circuits with hierarchical redundancies

For wafer scale integration, the concept of redundancy is important to yield enhancement and circuit repairability. In designing today's complex VLSI circuits, structured hierarchical design methodology in which a chip is partitioned into different levels of building blocks is generally preferred. The question naturally arises: Can hierarchy of redundancies be used to advantage? To maximize the circuit yield, we are therefore concerned with the size of the block at each level and the distribution of redundancies among blocks. This paper analyses the relationship between yield and the redundancy distribution for a two-level chip architecture with a given over-all redundancy overhead factor.     

Ultra-large scale integration

Ultra-large scale integration is governed by a hierarchical matrix of limits. The levels of this hierarchy can be codified as 1) fundamental, 2) material, 3) device, 4) circuit, and 5) system. Each level includes both theoretical and practical as well as analogical limits. Theoretically, thermal fluctuations impose a fundamental limit of several kT on switching energy. Scattering limited velocity and critical electric field establish a material limit on switching speed. Avoidance of punchthrough sets a device dimension limit. CMOS power-delay product defines a circuit limit. And, clock skew represents a system limit on ULSI. For conservative design margins, circuit limits project MOSFET channel lengths in the 0.4-0.2 µm range.     

Heterogeneous silicon integration by ultra-high vacuum wafer bonding

Heterogeneous integration of technologically important materials, such as SiC/Si, GaN/Si, Ge/Si, Si/nano-Si/Si, SiC-on-insulator (SiCOI), and ZrO₂/SiO₂/Si, was successfully made by ultra-high vacuum (UHV) wafer bonding. A unique, UHV bonding unit, especially designed to control interface structure, chemistry, and crystallographic orientation within narrow limits, was used to produce homophase and heterophase planar interfaces. In-situ thin-film-deposition capability in conjunction with the wafer bonding offered even more flexibility for producing integrated artificial structures. Prebonding surface preparation was critically important for the formation of strong bonded interfaces. The substrate-surface morphology was examined by atomic-force microscopy (AFM) prior to bonding. In-situ Auger spectroscopy measurements of surface chemistry were invaluable predictors of bonding behaviors. Plasma processing very effectively cleaned the substrates, achieving a near-perfect interfacial bond at the atomic scale. The integrity of the bonded interfaces was studied in the light of their structural and chemical characteristics analyzed by high-resolution, analytical electron microscopy.     

Comments, with reply, on `Future trends in wafer scale integration'by R.O. Carlson and C.A. Neugebauer

The commenter argues that the authors of the above paper (see ibid., vol.74, no.12, p.1741-1752, 1986) prematurely dismissed memory as a WSI candidate. He raises the valid point that WSI memory is easier to implement than WSI logic. He proposes a wafer virtual memory as particularly suitable for WSI, using a look-up table to keep track of good and bad RAM cell locations, and thus routing the addresses only to the good locations. The authors contend that while it may well be that memory is ideally suited to WSI for the proposed Chesley usage, it does not represent and overwhelming advantage over the equivalent printed wiring board implementation, and they state their reasons for this conclusion     

Future trends in digital telecommunication transmission networks

New technology is needed by digital transmission networks for the increased bandwidth, performance and reliability requirements of existing and future telecommunication services, such as broadband ISDN. Increased flexibility, automation and control are also major issues being addressed. The combination of these factors has led to the development of synchronous digital hierarchy (SDH) networks to replace existing asynchronous networks during the 1990s. These issues are reviewed and further developments to bandwidth-transparent optical networks indicated for the twenty-first century     

Direct wafer bonding of III-V compound semiconductors forfree-material and free-orientation integration

This paper describes the use of direct wafer bonding technique to implement the novel concept of “free-material and free-orientation integration” which we propose. The technique is applied for various wafer combinations of an InGaAsP material system, and the properties of the bonded structures are studied in terms of the crystalline and electrical characterization through transmission electron microscope, X-ray diffraction, and so on. This technique's advantage for use in the fabrication of lattice-mismatched structures is confirmed by the crystalline characterization, together with its second advantage of enabling bonded structures with an orientation mismatch, is investigated. The high crystalline quality of the bonded structures with both lattice and orientation mismatches is proved, and the electrical property of the bonded interface is examined for some of them. We show a practicability in a laser fabricated on a lattice- and orientation-mismatched structure by direct bonding. The results demonstrate the remarkable feasibility of using the direct wafer bonding technique to obtain integrated structures of material- and orientation-mismatched wafers with satisfactory quality     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.     

仅20元/台的不寻址机顶盒及其应用

经过多年发展和建设,恒湖有线电视台已拥有２　０００多用户,但因为处于经济落后地区,收费难一直困扰本台。大卫公司为了满足台里要求：去掉ＪＵＭＰＵＰ８００ ＣＡＴＶ／ ＭＭＤＳ寻址功能,采用仅２０元／台的不寻址机顶盒,前端不需投资一分钱,解决了收费难问题。待时机成熟后再升级为将无霸ＪＵＭＰＵＰ８００ ＣＡＴＶ／ＭＭＤＳ加解扰寻址系统。１　工作原理在有线电视分配网络中安装上经改装的分支器和ＪＵＭＰＵＰ不寻址机顶盒,即可实现对每个用户的电视信号进行控制。加扰在分支器中实现,解扰在ＪＵＭＰＵＰ不寻址机顶…     

Future trends in radio resource management for wireless communications

Recent growth in wirelessly connected devices shows no signs of slowing, and indeed with new services and new technologies waiting in the wings, usage of wireless terminals looks set to continue increasing rapidly. However, radio spectrum is finite and in a wirelessly connected future, new approaches to ensuring connectivity and quality of service are going to be needed. Radio resource management has an important part to play in ensuring that the very best is obtained from the finite resources available for radio communications in the future. This paper considers the characteristics of current end emerging wireless networks, and aspects of radio resource management that may offer the performance gains needed to ensure end-to-end quality of service is met.     

WGS1608-超大规模交叉连接芯片设计

交叉连接能力是ＳＤＨ系统的一致至关重要的功能指标,而交叉能力的强弱又完全依赖于交叉连接超大规模集成电路的能力。因而,武汉邮电科学研究院ＡＳＩＣ中心开发了ＷＧＳ１６０８这一１６＊８的叉连接超大规模集成电路,采用富士通０．３５μｍ工艺,规模为２２万门。本文介绍了ＷＧＳ１６０８的设计思想以及芯片的结构、特点和使用方法。     

Issues and trends in RF and mixed signal integration and partitioning

Over the last 40 years in the semiconductor industry, one of the most reliable truths has been that "thepath forward is through integration." Moore's law and its various derivatives and cousins have illustrated how greater integration has provided tremendous benefits in cost, power, size, and performance. While shrinking process lithography has been a critical enabler of this trend, we should remember that tremendous innovation in device technology, circuits, system architecture, computer aided design (CAD), packaging, and many other areas have been necessary as well. The exponential integration phenomenon has not been limited to memory and microprocessors: mixed signal and radio functions have also seen striking advances in integration over the last 20 years, from cell phones to wireless LANs, integrated "systemon-a-chip" (SOC) transceivers have become prevalent in the circuits conferences, journals, and - in some applications - have even made it into commercial mainstream products.