热阻网络法在半导体照明光源热分析中的应用

热阻网络法在传统热阻定义的基础上,简化了系统的计算模型。文章在分析半导体照明系统内部各器件热阻的基础上,提出了一种计算各点温度的热阻网络模型。利用一维热阻网络拓朴关系进行了热场的计算和分析,并与有限元仿真结果进行了对比。通过验证表明,采用该方法得到的结点温度与有限元仿真的结果相差不超过5%,模拟结果与热阻网络模型预测的结果吻合得很好,显示该模型具有较高的精确度。这种热阻网络拓朴分析技术可在某种程度上应用于发光二极管(LED)组件甚至复杂的照明系统的热学分析。     

混合集成电路常见装配结构热阻分析

从常规电子产品热设计基础理论的理解分析入手,结合实际应用,阐述了混合集成电路典型装配结构热阻的简便分析方法;绘制了多种典型结构的内热阻与发热芯片面积的关系曲线和外热阻与封装表面积的关系曲线;提出了通过典型结构热阻曲线分析产品芯片结温的方法,及相应问题的处理办法;对一般混合集成电路的非精确热设计有一定的参考意义。     

非晶硅薄膜晶体管的热阻模型

基于能量方程、热流方程和边界条件,推导出了非晶硅薄膜晶体管的沟道热阻模型。采用该模型可准确预估器件有源层内的平均温度。在沟道热阻模型的基础上,考虑器件间场氧化层和金属互联线的影响,建立了非晶硅薄膜晶体管的二维热阻模型。采用该模型可描述器件有源层内温度的横向分布,并快速预估沟道内的最高结温。最后,将模型预测结果与器件模拟仿真结果进行了对比,两者拟合良好。     

一种基于热阻网络的叠层芯片结温预测模型

提出了一种基于热阻网络的叠层芯片结温预测模型,该模型根据芯片内各组件的尺寸和热导率计算出对应的热阻,同时考虑了接触热阻和热量耦合效应,从而得到每层芯片在不同功耗情况下的结温预测值。在一个三芯片堆叠结构中,使用提出的方法对芯片结温进行预测,并与ANSYS仿真软件结果作比较,发现结温预测值的相对误差均小于4.5%。因此,该模型仅需根据芯片结构和材料参数,便可快速精确地估算出芯片在不同工作环境下的结温值。     

精简热模型在集成电路封装中的应用研究

探讨了为一款FBGA封装产品建立DELPHI型热阻网络的新方法。首先利用恒温法为芯片封装建立星型网络,在此基础之上求解支路耦合热阻值,构成DELPHI型热阻网络。经过仿真验证显示,所建立的两种DELPHI型热阻网络模型与详细热模型(DTM)的结温误差均在10%以内,从而具备较好的边界条件独立性。     

精简热模型在集成电路封装中的应用研究

探讨了为一款FBGA封装产品建立DELPHI型热阻网络的新方法。首先利用恒温法为芯片封装建立星型网络,在此基础之上求解支路耦合热阻值,构成DELPHI型热阻网络。经过仿真验证显示,所建立的两种DELPHI型热阻网络模型与详细热模型(DTM)的结温误差均在10%以内,从而具备较好的边界条件独立性。     

光纤传感器在全光网络安全及防范措施中的应用

在对全光网络存在的安全问题分析的基础上,总结了现存的攻击方法,讨论了光纤传感器在全光网络安全及防范措施中应用,在现有的理论模型基础上提出一种新型的全分布式光纤传感器模型,最后分析了该方案解决全光网络安全隐患的有效性.     

用于改善多指SiGeHBT热特性的变指间距设计方法研究

通过引入表示发射指之间热耦合程度的耦合热阻,建立了多指异质结双极晶体管(HBT)热阻模型.基于该模型,得 到了耦合热阻与指间距的变化关系,并用于器件指间距的设计.当耦合热阻均匀分布时,所对应的一套非等值的指间距值便 是器件温度均匀分布所要求的指间距值.用该方法得到热阻分布与热模拟得到的温度分布相吻合.但这种方法不必通过...     

微系统热阻模型研究及其应用

系统级封装(SIP)实现了高密度、高集成度封装技术,同时散热问题备受关注,热设计中芯片结温预测十分重要.本文采用有限元仿真方法,建立了一种自然对流环境下微系统热阻模型,并通过模型中热阻矩阵预测多芯片总功耗相同条件下的各芯片结温,同时利用热阻测试试验和有限元仿真方法对预测结温进行验证,结果表明热阻矩阵模型预测芯片结温与热阻测试试验和有限元仿真结果误差分别小于2%和5%.但同时发现该热阻矩阵模型的不通用性,对于总功耗变化的多芯片结温,预测结果偏差较大.通过不同总功耗下各热阻矩阵的函数关系建立拟合曲线并修正热阻矩阵模型,修正后的结环境热阻矩阵适用于不同总功率条件、各芯片不同功率条件下的芯片结温预测,预测结果与热阻测试试验中芯片结温和有限元仿真结果误差均小于5%.因此,提出的修正结环境热阻矩阵的方法可以快速且便捷地预测不同功率芯片的结温,并对器件的散热性能进行较为准确的预估.     

建立封装芯片热阻网络模型的方法研究

针对电子设备系统级热分析中封装芯片模型复杂程度与计算精度的矛盾,引入热阻网络法,替代系统级分析中封装芯片的详细物理模型;并以某PBGA封装芯片为例,进行两种建模方法的对比分析,同时介绍一种快速确定网络中热阻值的方法.结果表明,热阻网络等效方法具有模型简单、分析快速、准确度高的优点,在系统级热分析中可完全替代详细的物理模型.     

多发光区大功率激光器的热特性分析

通过电学温敏参数法测得多发光区大功率激光器瞬态加热响应曲线,利用结构函数法给出了多发光区激光器热阻构成,分析了多发光区激光器热特性。通过串并联热阻网络模型刻画了单发光区、两发光区、四发光区激光器的热阻构成,给出了激光器芯片热阻与发光区个数之间的定量关系。实验结果表明,不同发光区激光器的芯片级热阻随着发光区数量的增加成比例减小,而封装级热阻不变,这对激光器热设计提供了重要的参考准则。     

Thermal resistance of side by side multi-chip package: Thermal mode analysis

The thermal mode analysis is used in this paper to optimize the thermal management with optimal locations and chip sizes for multi-chip package. The average thermal resistance is defined and analyzed. The spreading thermal resistance can be expanded into Fourier series so that the thermal modes can be established. For the infinite thermal modes, only a few terms are needed to be considered due to the rapid convergence of solution. The optimal locations and chip sizes can then be determined by using the first few modes to reduce the thermal resistance as minimal as possible. The optimal locations have the cosine wave property so that the wave nodes might be the suitable sites. On the other hand, the optimal chip sizes have the cardinal sine property which decays monotonously. For given optimal locations, the optimal chip sizes are determined by certain modes. These special modes can be used to analyze the range of optimal locations and chip sizes.     

New method to measure emitter resistance of heterojunction bipolar transistors

The in third-order intermodulation as a function of emitter current in a bipolar transistor is exploited to find emitter Ohmic resistance. The measurement can be carried out using only low-cost equipment and a scalar receiver. Results for an heterojunction bipolar transistor (HBT) are compared with those found using a vector network analyzer and a sophisticated extraction algorithm. The method is extended to simultaneously determine thermal resistance, R/sub TH/, and to obtain a most precise estimate of emitter resistance.     

Interfacial thermal resistance and temperature dependence of threeadhesives for electronic packaging

The thermal resistance and its temperature dependence was measured for three industrial adhesives used for electronic packaging. Measurements were made by the laser-flash method from room temperature to 300°C. The samples were in the form of sandwiches consisting of two platelets of silicon carbide-reinforced aluminum (AlSiC) bonded together with the adhesives. The total thermal resistance of the bond (the sum of the bulk thermal resistance of the adhesive and the resistances at the two interfaces) was calculated from the thermal response of the sandwich subjected on one side to a single laser-flash. The total thermal resistance was found to decrease with increasing temperature. The bulk thermal resistance of the adhesive, calculated from its thickness and independently determined thermal conductivity, was found to be relatively independent of temperature. The interfacial resistance at the AlSiC interfaces, depending on the adhesive, ranged from about 60 to 80% of the total resistance decreasing to about 50% of the total interfacial resistance at 300°C. For two of the adhesives considered in this study, the interfacial thermal resistances for the AlSiC/adhesive interfaces were found to be considerably higher than those found in an earlier study of Si/adhesive interfaces     

LDMOS热阻的电学法测试与分析

基于结构函数理论,运用电学测试法,提取封装LDMOS导热路径上各层材料的热阻值,以及管壳与恒温平台之间的接触热阻值。对各层热阻进行分析,发现焊料层的热阻远大于理论值,提出了一种减小焊料层热阻的方法。改变管壳与恒温平台的接触情况,分别测出不同接触情况下的热阻值,对比发现接触情况会影响结到壳热阻的大小,提出了减小接触热阻的方法。     

用扫描热显微镜研究材料表面微区热导分布

从集总参数模型出发,初步分析了热敏电阻型热探针的热传导机制和热物性测量机理,说明了扫描热探针的信号与样品表面温度、样品与探针间的热阻以及样品热导率等因素有关。在不同的工作条件下,可分别用以进行表面的温度分布和微区热导分布等热参数的测量。选定Ｓｉ－ＳｉＯ２标准样品,定性地讨论了表面形貌和样品热导率对测量结果的影响。把扫描热显微镜用于复合材料研究,得到的热像图提供了微区热导分布的信息。     

Thermal performance of collector-up HBTs for small high-power amplifiers with a novel thermal via structure underneath the HBT fingers

We will describe the thermal performance of a special heterojunction bipolar transistor (HBT) structure for mobile communication systems, called a collector-up HBT. We calculated the thermal resistance between the HBT fingers and the bottom surface of a GaAs substrate using a finite element method (FEM). The results suggest that the thermal resistance of collector-up HBTs with thermal via structures can be reduced by 64% compared to the thermal resistance of ordinary emitter-up HBTs. They also show that the thickness of the InGaP emitter layer effects the thermal resistance of, and the temperature distribution in, the collector fingers of collector-up HBTs. Even though the thermal resistance of collector-up HBTs can be much smaller than that of emitter-up HBTs, a thermal interaction between the collector fingers still exists in multi-finger structures. We analyzed the temperature distribution in the collector fingers of a four-finger HBT structure and found that the thickness of the plated heat sink (PHS) was not sufficient to reduce the thermal interaction between the HBT fingers, and that optimization of the HBT location was needed to minimize the thermal interaction. We also found that the thickness of the InGaP emitter layer was the most important parameter for reducing thermal resistance, even in four-finger HBT structures. These calculation results can be used to reduce the temperature of collector-up HBTs and the temperature differences between the HBT fingers in the development of power amplifiers with collector-up HBTs.     

Thermal resistance analysis by induced transient (TRAIT) method forpower electronic devices thermal characterization. I. Fundamentals andtheory

In this paper, a careful theoretical analysis of the thermal dynamics of an electronic device and its package was carried out in order to study the problem of the equivalent thermal circuit implementation. It was found that the device temperature evolution in time is ruled by an infinite and convergent series of time constants. The knowledge of the first n terms of the time-constant spectrum obtained from the temperature transient measurements allows the complete characterization of a suitable and reliable equivalent thermal circuit structured as a Cauer low-pass network with n cells. The total thermal resistance is therefore evaluated as a sum of several contributions due to given parts of the whole system. The techniques allowing the physical identifications of these contributions are also discussed. Furthermore, the influence of plastic coverage on the device thermal behavior is taken into account. The proposed characterization method is also applied to one-dimensional (1-D) multilayered simulated structures in order to study the influence of the number of time constants used for the analysis and effects of local defects or modifications of the material thermal properties