MOS characteristics of ultrathin SiO2 prepared byoxidizing Si in N2O

MOS characteristics of ultrathin gate oxides prepared by furnace oxidizing Si in N₂O have been studied. Compared to control oxides grown in O₂, N₂O oxides exhibit significantly improved resistance to charge trapping and interface state generation under hot-carrier stressing. In addition, both charge to breakdown and time to breakdown are improved considerably. MOSFETs with N₂O gate dielectrics exhibit enhanced current drivability and improved resistance to g_m degradation during channel hot-electron stressing     

Electrical characteristics of TiB2 for ULSI applications

The work function of TiB₂ was measured using Fowler-Nordheim tunneling in MOS capacitors, Schottky diode current measurements, capacitance-voltage techniques, and contact resistance. The resulting data place the Fermi level of TiB₂ about 0.9 eV below the silicon conduction band. Given this barrier height, Schottky diodes of TiB₂/p-Si exhibit ohmic characteristics, but the contact resistance of TiB₂ to n⁺ junctions is an order of magnitude higher than the generally desired value. Boron outdiffusion from TiB₂ into underlying silicon was observed at temperatures of 1000°C and greater. Boron diffusion from TiB₂ into silicon above 1000°C is enhanced compared to the conventionally accepted value of the boron diffusivity     

The characteristics of polysilicon oxide grown in pureN2O

This work reports on the characteristics of polysilicon oxide grown in pure N₂O (N₂O-grown polyoxide). The obtained polyoxide has a desirable polarity asymmetry of J-E characteristic, i.e., a lower leakage current and a higher breakdown electric field, which are ideal for the nonvolatile memory application, when the top electrode is positively biased. The asymmetry is due to the smoother surface of the N₂O-grown polyoxide. Comparing to conventional polyoxides, the N₂O-grown polyoxide has a lower electron trapping rate and a larger Q_bd, which are attributed to the incorporated nitrogen at the polyoxide/poly-1 interface. The centroids of trapped charges of the N₂O-grown polyoxide are more away from the polyoxide/poly-1 interface and this affects the polarity dependence of trapping     

Effect of N2O nitridation on the electrical properties of MOS gate oxides

Furnace annealing in N₂O is a convenient technique for improving the reliability of thermal oxides without significant modifications of the process flow. We investigate the impact of N₂O nitridation on MOSFET device performance, assessing the various factors contributing to the observed degradation of electron mobility. Estimates based on low-frequency C-V and charge pumping measurements show that nitridation causes a significant increase of the interface trap density in the vicinity of the conduction band. Interface traps contribute a parasitic component to the gate-channel capacitance, thus leading to an overestimate of the inversion charge. This effect accounts for a substantial fraction of the mobility degradation which is observed for the nitrided devices. The remaining degradation can be ascribed to an enhancement of Coulomb scattering, maybe due to differences in dopant segregation, and to a change of the surface roughness characteristics.     

Effects of nitridation pressure on the characteristics of gatedielectrics annealed in N2O ambient

Effects of N₂O pressure during oxynitridation on the characteristics of ultrathin gate dielectrics have been investigated. Reoxidation in N₂O ambient showed three distinguished oxidation regions as a function of tube pressure; that is, enhancement at 10-40 torr, retardation at 40-100 torr, and enhancement at 100-600 torr. The N₂O-nitridation at 40 torr incorporated much less nitrogen in oxide bulk than that at near-atmospheric pressure. The 40 torr N₂O-nitridation case exhibited about 70% of nitrogen incorporation at the Si/SiO₂ interface compared to that of the 600 torr N₂O-nitridation case. The low-pressure N₂ O-nitridation at 40 torr results in improvement of TDDB of gate dielectrics and the transconductance of nMOSFETs compared to the nitridation at near-atmospheric pressure. These data suggest that low pressure oxynitridation should be more recommendable for device application     

Enhanced reliability for low-temperature gate dielectric of MOS devices by N2O or NO plasma nitridation

Silicon MOS capacitors fabricated solely by low-temperature processes (under 600 °C) are treated with nitridation using N₂O or NO plasma. Their properties are investigated at room temperature under high-field stress. It is found that both kinds of plasmas are effective in improving the gate-oxide hardness against stress-induced damage, which is characterized by a smaller shift in flatband voltage and smaller increase in interface states after the stress. Moreover, NO-nitrided device shows better performance than N₂O-nitrided one. These results show that plasma nitridation has positive effects on the reliability of low-temperature-fabricated devices, which play an important role in flat-panel display systems on glass.     

Nitrogen bonding configurations near the oxynitride/silicon interface after oxynitridation in N2O ambient of a thin SiO2 gate

The identification of the bonding environments and their progressive modifications upon reaching the oxynitride/silicon interface, in a SiO₂/SiO_xN_y/Si structure, have been investigated by means of X-ray photoemission spectroscopy (XPS). The SiO₂ film was grown at 850 °C by means of a mixed dry-steam process, followed by a 60 min, 950 °C furnace oxynitridation in N₂O gas. A depth profile analysis was carried out by a progressive chemical etching procedure, reaching a residual oxide thickness of about 1.2 nm. XPS analysis of the Si 2p and N 1s photoelectron peaks pointed out that the chemistry of the oxynitride layer is a rather complex one. Four different nitrogen bonding environments were envisaged. Both the overall nitrogen content, which rises up to 2.5%, and its bonding configurations are progressively changing while moving towards the silicon interface.     

SiSiO2 interface state spectroscopy using MOS tunneling structures

This paper provides a critical review and classification of the studies of SiSiO₂ interface state parameters and energy distributions by means of MOS tunneling in structures with ultrathin SiO₂ layers (10–100 Å). Suggestions are made of experiments that will help to elucidate the importance of materials and processing conditions on these states, and to separate the various mechanisms involving charge exchange with the metal, the conduction band, and the valence band of the semiconductor.     

Electron transport through broken down ultra-thin SiO2 layers in MOS devices

When the gate insulator of a metal–oxide–semiconductor structure is subjected to electrical stress, traps or defects are progressively generated inside the oxide that eventually lead to the formation of a low-resistance conducting path between the electrodes. The occurrence of such event can be detected either as a gradual or as a sudden change in the system’s conductance and is associated with the appearance of a localized conduction mechanism in parallel with the area-distributed tunneling current. According to the magnitude and shape of the resulting current–voltage characteristic, the failure mode is usually referred to as soft or hard breakdown. However, because of the random nature of the phenomenon, interpretation and modelling of the electron transport mechanism involved has turned out to be very challenging from the physical point of view. Several models have been proposed to this aim, which can be classified basically according to the underlying mechanism: junction-like, hopping, percolation and tunneling conduction. Within this latter mechanism we can mention direct, Fowler–Nordheim, trap-assisted, resonant, inelastic tunneling and point contact conduction. In this paper, after an overview of a variety of physical and engineering aspects of post-breakdown, we critically examined the foundations and limitations of the proposed conduction models in the light of others and ours experimental results, putting special emphasis on those approaches providing final closed expressions.     

Transport model in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications

The origin of enhanced injection in n⁺⁺-poly/SiO_x /SiO₂/p-sub MOS capacitors under accumulation is investigated. Starting from experimental evidences as the structural homogeneity of the off-stochiometric oxide and the temperature dependence of current in n⁺⁺-poly/SiO_x/p-sub capacitors, we developed a new transport model. In this picture, transport consists on the Poole-Frenkel and multistep tunneling of the SiO_x barrier and the Fowler-Nordheim (FN) tunnel of the SiO ₂ barrier, the latter definitely limiting the current flowing through the MOS. The model explains how the presence of two barriers and an accelerating electric field in the SiO_x gives rise to the injection enhancement, respect to the case of a single conventional n ⁺⁺-poly/SiO₂ barrier. In fact, after the trap-assisted tunnel of the first barrier, the electron arrives at the SiO_x/SiO₂ interface with an excess energy furnished by the electric field. There, it sees an FN barrier lower than in the conventional case. Experiment and model calculations are in excellent agreement     

Highly suppressed boron penetration in NO-nitrided SiO2for p+-polysilicon gated MOS device applications

In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiO₂ in suppressing boron penetration for p⁺-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage shift, decrease in inversion capacitance (due to polysilicon depletion effect), impact on interface state density, and charge-to-breakdown. Results show that NO-nitrided SiO₂, as compared to conventional thermal SiO₂, exhibits much higher resistance to boron penetration, and therefore, is very attractive for surface channel PMOS technology     

Novel low-temperature C-V technique for MOS doping profiledetermination near the Si/SiO2 interface

An inverse modeling technique for doping profile extraction from MOS C-V measurements is presented. The method exploits the “kink” effect observed near flat bands in low-temperature C-V curves to accurately estimate the dopant concentration at the oxide-silicon surface. The inverse modeling approach, based on a self-consistent Schrodinger-Poisson solver, overcomes the limitations of previous analytical methods. The accuracy of the doping extraction is demonstrated by successfully reconstructing doping profiles from simulated C-V curves, including abrupt variations of doping in the vicinity of the oxide interface. When applied to experimental data from boron- and phosphorus-doped samples, the technique is shown to provide a substantial improvement in resolution with respect to room-temperature C-V measurements     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

Pre- and post-BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale

In this work, the electrical properties of fresh and stressed HfO₂/SiO₂ gate stacks have been studied using a prototype of Conductive Atomic Force Microscope with enhanced electrical performance (ECAFM). The nanometer resolution of the technique and the extended current dynamic range of the ECAFM has allowed to separately investigate the effect of the electrical stress on the SiO₂ and the HfO₂ layer of the high-k gate stack. In particular, we have investigated this effect on both layers when the structures where subjected to low and high field stresses.     

Enhanced injection in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications: experiment

In this paper, n⁺⁺-poly/SiO_x/SiO₂/p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiO_x films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiO_x film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n⁺⁺ -poly/SiO_x/SiO₂/p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiO_x films is proposed. In SiO_x films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiO_x/SiO₂ interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiO_x films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap     

Hot-carrier injections in SiO2

We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (< 5 nm) gate-oxide.     

SiO2隧穿层不同气氛氮化退火对MONOS存储器性能的改善

Metal–oxide–nitride–oxide–silicon(MONOS)capacitorswiththermallygrownSiO2asthetunnellayer arefabricated,andtheeffectsofdifferentambientnitridation(NH3,NOandN2O)onthecharacteristicsofthememory capacitors are investigated.The experimental results indicate that the device with tunnel oxide annealed in NO ambient exhibits excellent memory characteristics,i.e.a large memory window,high program/erase speed,and good endurance and retention performance(the charge loss rate is 14.5%after 10 years).The mechanism involved isthatmuchmorenitrogenisincorporatedintothetunneloxideduringNOannealing,resultinginalowertunneling barrier height and smaller interface state density.Thus,there is a higher tunneling rate under a high electric field and a lower probability of trap-assisted tunneling during retention,as compared to N2O annealing.Furthermore,compared with the NH3-annealed device,no weak Si–H bonds and electron traps related to the hydrogen are introduced for the NO-annealed devices,giving a high-quality and high-reliability SiON tunneling layer and SiON/Si interface due to the suitable nitridation and oxidation roles of NO.     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Formation of high quality storage capacitor dielectrics by in-siturapid thermal reoxidation of Si3N4 films inN2O ambient

This letter reports on a novel reoxidation technique for SiO₂ /Si₃N₄ (ON) stacked films by using N₂ O as oxidant. Effect of in-situ rapid thermal N₂O reoxidation (RTNO) on the electrical characteristics of thin ON stacked films are studied and compared with those of in-situ rapid thermal. O ₂ reoxidation (RTO). Prior to reoxidation, the Si₃N₄ film was deposited by rapid thermal chemical vapor deposition (RT-CVD) using SiH₄ and NH₃. Results show that RTNO of the Si₃N₄ films significantly improves electrical characteristics of ON stacked films in terms of lower leakage current, suppressed charge trapping, reduced defect density and improved time-dependent-dielectric-breakdown (TDDB), as compared to RTO of the Si₃N₄ films