超高速数字集成电路——ECL

一般认为,平均传输延迟时间大于50毫微秒的电路,称为低速电路;10～50毫微秒之间者称为中速电路;2～10毫微秒之间者称高速电路;小于2毫微秒则称为超高速电路.改进的TTL电路可达高速.工程技术人员一直在努力寻找比普通TTL电路速度更高     

一种高速大电流开关驱动器的设计与实现

设计并实现了一种高速大电流的开关驱动器,可用于驱动PIN开关以及IGBT开关等.开展了系统结构、电路和版图技术研究,并采用亚微米CMOS标准工艺进行设计和制造.通过采用一种带隙基准结构提供偏置的方式使电路兼容TTL和CMOS输入,保证良好的温度特性;通过采用传输门功率驱动电路实现三态控制,解决了高速应用时电容馈通效应问题.详细设计了TTL输入转换电路、基准和偏置电路、三态输出和功率驱动等电路;基于0.6 μm CMOS工艺重点设计了高速驱动器中功率开关版图.该高速大电路开关驱动器产品的传输速度达到了25 ns,驱动电流达500 mA.     

晶体管分流限制饱和TTL电路

本文提出并讨论分析了一种晶体管分流限制饱和TTL电路.该方法采用了双发射极倒相放大管结构,并在第二发射极和输出管集电极之间接入限制饱和回路以加速截止过程.计算和实验表明,电路的平均时延比标准TTL电路降低了一个数量级.晶体管分流电路保留了标准TTL电路的全部优点而无需改变制造工艺,且不必增加电路元件.在同一条制造线上,通过与肖特基限制饱和TTL电路的对比说明,该电路室温时延接近后者,但具有更好的噪声余量和高温性能,而且也更适宜于双极型集成电路制造工艺.     

双极型电路通用综合方法与电路三要素理论

该文在电路三要素(信号,网络和负载)理论的基础上提出双极型电路通用综合方法。文中首先引入适用于电压型和电流型电路的广义二值信号,推导出源信号和负载简化定理。由此分析各单元电路结构和推导出相应的元件级电路表达式,进一步找出一种新的电路实现方式。在此基础上设计出新的低压TTL和多射型ECL元件级电路。最后经过电路实验证明理论的正确性。     

在大多数系统中高速C-MOS逻辑电路将取代TTL

一种新型的低功耗高速C-MOS芯片,作接口电路用,要比TTL芯片更加优越。     

用氧化物隔离法使STTL高性能化

本文研究了采用氧化物隔离工艺的高速低功耗肖特基晶体 管-晶体管 逻辑(TTL)电路。在此工艺中,晶体管被氧化物所包围着。特别是由于采用发射极的四个边中相对应的两边与氧化墙相邻接的隔离结构,所以能够缩小晶体管的尺寸,减小寄生电容。同时,由于采用了浅结结构,因而获得的电流增益·带宽乘积f_T为5千兆赫。电路方面,在原来的肖特基TTL电路基础上增加了一级放大,构成了三级结构。输入元件采用了二极管。因此,提高了电路的噪声容限。采用此工艺的肖特基电路系列的速度比以往的低功耗肖特基TTL电路快75％、功耗为标准肖特基TTL电路的1/4。     

集成超高速ECL电路现状

大家知道,数字电路有饱和型和非饱和型两种,在实现高速方面,饱和型以TTL为代表,非饱和型以发射极耦合逻辑(ECL)为代表。功耗方面以TTL较低,速度方面以ECL较高。因此ECL电路成为超高速电路的重要方式,几年来有了较大的发展,见表1所示。目前ECL电路的应用到计算机中的水平和生产水平是传递延迟为1毫微秒的电路。目前的研究水平是O.3～O.5毫微秒的ECL电路。目前国外应用超高速ECL电路的高性能计算机有IBM公司的360/85、370/195,CDC公司的7600、星—100,通用电气公司的655计算机等。     

高速中规模集成数字频率合成器

本文介绍的新型高速中规模集成数字频率合成器是由高速ECL集成的前置分频器(脉冲吞除计数器)、中速TTL集成的二-十进制同步可逆可预置计数器、数字集成鉴相器与环络滤波器,集成负阻压控振荡器以及一些TTL电路组成.逻辑设计打破了过去习惯采用的"九置定"、"九读出"法,而采用"零置定"、"零读出"的新方法.这样便于和计算机直接连接进行实时     

一种快速多用途TD-TTL弛豫振荡器

本文提出TD-TTL组合弛豫振荡电路.由于综合利用了两种快速器件(隧道二极管与高速晶体管-晶体管逻辑)的特点,又加上特有的反馈网络,因而呈现出一系列优越的电学性能.诸如波形好、高速、宽带频率变换、便于程控以及灵活多变的电路功能等. 本文研究了TD与TTL接口电平的匹配关系,分析计算了电路的振荡周期,列出了性能特点,给出了应用实例,指出了应用前景.     

CMOS集成电路使用注意事项

数字集成电路可分为TTL和MOS电路(目前以CMOS为主)。TTL以高速度见长,MOS电路则以低功耗著称。高速CMOS是CMOS的第二代产品,同时有低功耗的特点,因此得到了广泛应用。本文介绍CMOS集成电路在使用过程中的几点注意事项。一、使用之前认真阅读产品说明书或有关资料,了解管脚分布情况及其极限参数。     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

High-speed bipolar logic circuits with low power consumption for LSI-a comparison

Various high-speed bipolar logic circuits (CML, FECL, NTL, TTL, STL) are investigated and compared which exhibit gate delays far below 1 ns, even at a very low power dissipation per gate (e.g. 0.1 mW). Therefore, these circuits are best suited for LSI. It is shown that, by tailoring the circuit components (transistors, Schottky diodes) to the power dissipation P, the expected increase of the gate delay t/SUB D/ according to t/SUB D/~1/P can be shifted to surprisingly low values of P. Further, the simulations show that the Schottky clamp technique has considerable advantages concerning the switching speed at very low power dissipations, compared with the current-mode logic known to be fast. The results are explained by simple calculations.     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an xor gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43–45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a$2^7!-!1$sequence length. The circuits were fabricated in a SiGe BiCMOS technology with$f _T = 120~hboxGHz$. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively.     

一种新型TTL非门电路的设计

叙述了一种新型ＴＴＬ非门电路的设计思路，电路工作原理和调试实验，人析了其集成的可行性，说明了新电路如何克服现有的ＴＴＬ非门电路自身的弱点，使其工作更加稳定可靠，这种新型ＴＴＬ门电路的应用提高了数字逻辑电路工作的稳定性。     

Low-voltage high-speed Schmitt trigger and compact window comparator

Gates with input hysteresis are often necessary in circuits operating in noisy environments. Described is a very simple CMOS Schmitt trigger circuit, well suited for low-voltage and high-speed applications. The circuit also allows the construction of a very compact window comparator.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.