Monolithic feedback low noise X-band amplifiers using 0.5-μmGaAs MESFETs: comparative theoretical study and experimentalcharacterization

Three different feedback low-noise-amplifier (LNA) circuit topologies for simultaneous noise and power matching are theoretically investigated and compared for the X-band application. The smallest minimum noise figure (NF_min) is shown to be achieved by the common source parallel feedback (CSPF) topology, while the common source series feedback (CSSF) topology exhibits the best overall performance. Experimentally, a CSSF three-stage LNA has been fabricated using 0.5-μm-gate GaAs MESFETs and systematically characterized. In this LNA circuit, an optimal series feedback for noise figure, gain, and stability is implemented via a proper choice of the short stub length. The size of the fabricated monolithic microwave integrated LNA chip is only 1 mm²/stage. The measured gain varies from 22.0 to 23.0 dB in the frequency range of 8 to 10 GHz, with good flatness. The input/output voltage standing wave ratios are less than 2 and 1.43, respectively. The noise figure of the three-stage LNA is less than 2.6 dB. These measured data are sufficient for practical applications and are also in good agreement with simulated results     

0.3 dB minimum noise figure at 2.5 GHz of 0.13 μm Si/Si0.58Ge0.42 n-MODFETs

RF and microwave noise performances of strained Si/Si_0.58 Ge_0.42 n-MODFETs are presented for the first time. The 0.13 μm gate devices have de-embedded f_T=49 GHz, f_max =70 GHz and a record intrinsic g_m=700 mS/mm. A de-embedded minimum noise figure NF_min=0.3 dB with a 41 Ω noise resistance R_n and a 19 dB associated gain G_ass are obtained at 2.5 GHz, while NF_min=2.0 dB with G_ass=10 dB at 18 GHz. The noise parameters measured up to 18 GHz and from 10 to 180 mA/mm with high gain and low power dissipation show the potential of SiGe MODFETs for mobile communications     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's     

Noise modeling and SiGe profile design tradeoffs for RFapplications [HBTs]

This paper investigates SiGe profile design tradeoffs for low-noise RF applications at a given technology generation (i.e., fixed minimum feature size and thermal cycle). An intuitive model relating structural parameters and biases to noise parameters is used to identify the noise limiting factors in a given technology. The noise performance can be improved by pushing more Ge into the base and creating a larger Ge gradient in the base. To maintain the SiGe film stability, the retrograding of the Ge into the collector has to be reduced, leading to a stronger f_T-I_C roll-off at high injection. Two low-noise profiles were designed and fabricated explicitly for improving minimum noise figure (NF_min) without sacrificing gain, linearity, frequency response, or the stability of the SiGe strained layer. A 0.2 dB NF_min was achieved at 2.0 GHz with an associated gain (G_assoc) of 13 dB     

Frequency-Thermal Characterization of On-Chip Transformers With Patterned Ground Shields

Extensive studies on the performance of on-chip CMOS transformers with and without patterned ground shields (PGSs) at different temperatures are carried out in this paper. These transformers are fabricated using 0.18-mum RF CMOS processes and are designed to have either interleaved or center-tapped interleaved geometries, respectively, but with the same inner dimensions, metal track widths, track spacings, and silicon substrate. Based on the two-port S-parameters measured at different temperatures, all performance parameters of these transformers, such as frequency- and temperature-dependent maximum available gain (G_max), minimum noise figure (NF_min), quality factor (Q₁) of the primary or secondary coil, and power loss (P_loss) are characterized and compared. It is found that: 1) the values of the G_max and Q₁ factor usually decrease with the temperature; however, there may be reverse temperature effects on both G _max and Q₁ factor beyond certain frequency; 2) with the same geometric parameters, interleaved transformers exhibit better low-frequency performance than center-tapped interleaved transformers, whereas the center-tapped configurations possess lower values of NF_min at higher frequencies; and 3) with temperature rising, the degradation in performance of the interleaved transformers can be effectively compensated by the implementation of a PGS, while for center-tapped geometry, the shielding effectiveness of PGS on the performance improvement is ineffective     

60-GHz noise performance of ion-implanted InxGa1-xAs MESFET's

The authors report the 60-GHz noise performance of low-noise ion-implanted In_xGa_1-xAs MESFETs with 0.25 μm T-shaped gates and amplifiers using these devices. The device noise figure was 2.8 dB with an associated gain of 5.6 dB at 60 GHz. A hybrid two-state amplifier using these ion-implanted In_xGa_1-x As MESFETs achieved a noise figure of 4.6 dB with an associated gain of 10.1 dB at 60 GHz. When this amplifier was biased at 100% I _dss, it achieved 11.5-dB gain at 60 GHz. These results, achieved using low-cost ion-implantation techniques, are the best reported noise figures for ion-implanted MESFETs     

Investigation of Thermal Noise in UTB GOI and SOI Devices

The thermal-noise performances of ultrathin-body silicon-on-insulator (SOI) and germanium-on-insulator (GOI) devices are investigated and compared through simulation in this paper. The figures-of-merit for noise characteristics are considered in terms of the minimum of noise figure (NF_min)and equivalent noise resistance (R_n). GOI devices exhibit better noise performance over SOI counterparts. The reduction in the supply voltage brings more distinct improvements of the noise performance of GOI devices. The dependence of noise parameters on the film thickness and spacer length is also analyzed. The results demonstrate that GOI devices are more suitable for RF and low-noise applications.     

Microwave Performance of Double δ-Doped High Electron Mobility Transistor With Various Lower/Upper Planar-Doped Ratio Designs

The microwave noise, power, and linearity characteristics of pseudomorphic high electron mobility transistors (pHEMTs) with various lower/upper planar delta-doped ratios were systematically evaluated and studied. By varying the lower/upper delta-doped ratio from 1:1 to 1:4, both Schottky gate turn-on voltage V_ON and breakdown voltage V_BR were reduced. In addition, higher upper delta-doped design is effective in improving the device current density, transconductance, output power, and power-added efficiency; however, this design also scarified the flatness of transconductance distribution and Schottky performance, resulting in a degradation of device linearity. As to the noise performance, after increasing the upper delta-doped concentration by more than 2 times 10¹² cm^-2, the minimum noise figure NF_min can be reduced to a stable range, and higher current density cannot efficiently improve the noise performance. Although the 1:4 design provided the largest power density of pHEMT, its high gate leakage current at high input power swing limited its linearity, and 1:3 design achieved the best linearity performance.     

Analytical Determination of MOSFET's High-Frequency Noise Parameters From NF50 Measurements and Its Application in RFIC Design

An analytical method, along with closed-form solutions, to determine high-frequency (HF) noise parameters of the MOSFET from its noise figure (NF) measurements with an arbitrary source impedance is presented and experimentally verified. This method allows for the determination of the minimum noise figure, NF_min, equivalent noise resistance, R_n, and optimum source admittance Y_opt , of MOSFET directly from a single high-frequency 50-Omega noise figure measurement and a model characterization based on the transistor's measured scattering parameters. The proposed method can accurately predict the noise parameters of deep-submicron MOSFETs, and hence is useful in the design of low-noise radio-frequency integrated circuits (RFICs). Application of the proposed method in the design of CMOS RF low-noise amplifiers (LNAs) is also discussed     

A new method for on wafer noise measurement

A method for measuring the noise parameters of MESFETs and HEMTs is presented. It is based on the fact that three independent noise parameters are sufficient to fully describe the device noise performance. It is shown that two noise parameters, R_n and |Y_OPT|, can be directly obtained from the frequency variation of the noise figure F₅₀ corresponding to a 50 Ω generator impedance. By using a theoretical relation between the intrinsic noise sources as additional data, the F₅₀ measurement only can provide the four noise parameters. A good agreement with more conventional techniques is obtained     

An experimental study of carrier heating on channel noise in deep-submicrometer NMOSFETs via body bias

In this paper, RF noise in 0.18-mum NMOSFETs concerning the contribution of carrier heating and hot carrier effect is characterized and analyzed in detail via a novel approach that modulates the channel carrier heating and number of hot carriers using body bias. We confirm qualitatively a negligible role of hot carrier effect on the channel noise in deep-submicrometer MOSFETs. For a device under reverse body bias (V_b), even though the increase in hot carrier population is clearly characterized by dc measurements, the device high-frequency noise is found to be irrelevant to the increase in the channel hot carriers. Experimental results show that the high-frequency noise is slightly reduced with the increase in |V_b|, and can be qualitatively explained by secondary effects such as the suppression of nonequilibrium channel noise and substrate induced noise. The reduction of NF_min and R_n with the increase in |V_b| may provide a possible methodology to finely adjust the device high-frequency noise performance for circuit design     

Super-low-noise performance of direct-ion-implanted 0.25-μm-gateGaAs MESFET's

The authors report on advanced ion implantation GaAs MESFET technology using a 0.25-μm `T' gate for super-low-noise microwave and millimeter-wave IC applications. The 0.25×200-μm-gate GaAs MESFETs achieved 0.56-dB noise figure with 13.1-dB associated gain at 50% I_DSS and 0.6 dB noise figure with 16.5-dB associated gain at 100% I_DSS at a measured frequency of 10 GHz. The measured noise figure is comparable to the best noise performance of AlGaAs/GaAs HEMTs and AlGaAs/InGaAs/GaAs pseudomorphic HEMTs     

Noise performance of low power 0.25 micron gate ion implantedD-mode GaAs MESFET for wireless applications

We report on the noise performance of low power 0.25 μm gate ion implanted D-mode GaAs MESFETs suitable for wireless personal communication applications. The 0.25 μm×200 μm D-mode MESFET has a f_t of 18 GHz and f_max of 33 GHz at a power level of 1 mW (power density of 5 mW/mm). The noise characteristics at 4 GHz for the D-mode MESFET are F_min=0.65 dB and G_assoc =13 dB at 1 mW. These results demonstrate that the GaAs D-mode MESFET is also an excellent choice for low power personal communication applications     

Half-micrometer gate-length ion-implanted GaAs MESFET with 0.8-dBnoise figure at 16 GHz

Ion-implanted GaAs MESFETs with half-micrometer gate length have been fabricated on 3-in-diameter GaAs substrates. At 16 GHz, a minimum noise figure of 0.8 dB with an associated gain of 6.3 dB has been measured. This noise figure is believed to be the lowest ever reported for 0.5- and 0.25-μm ion-implanted MESFETs, and is comparable to that for 0.25-μm HEMTs at this frequency. By using the Fukui equation and the fitted equivalent circuit model, a K_f factor of 1.4 has been obtained. These results clearly demonstrate the potential of ion-implanted MESFET technology for K-band low-noise integrated circuit applications     

A temperature noise model for extrinsic FETs

A resistor temperature noise model for FETs has been successfully applied to extrinsic FETs to predict the frequency dependence of minimum noise figure F_min and associated gain G_Aopt. The model gives a fixed relationship between F_min and G_Aopt with one fitting parameter T_d. An extensive comparison to published results shows that the majority of FETs can be modeled with effective T_d values (the temperature of the output resistor) between 300 and 700 K for all of the frequencies (8 to 94 GHz), gate lengths (0.8 to 0.1 μm), and material types examined. The analysis shows that InP-based MODFETs exhibit significantly lower F_min and higher G_Aopt than conventional and pseudomorphic GaAs-based MODFETs of the same gate length. The results suggest a high F_max is a key factor for low noise figure     

BER expressions for differentially detected π/4 DQPSK modulation

Closed form bit-error rate (BER) expressions for differentially detected π/4-shifted differentially encoded quadrature phase-shift keying (QPSK) modulation (π/4 DQPSK) are derived for both additive white Gaussian noise (AWGN) and Rayleigh-fading channels. The derivations are carried out in an exact and most general manner in that in-phase (I) and quadrature (Q) channel bit-error probabilities P_cl and P_cQ are separately obtained in terms of the same-quadrature and cross-quadrature noise Correlation functions, including a measure of noise nonstationarity. We then specialize the general expressions for uncorrelated noise and equal noise powers in successive symbol periods to obtain a useful bit-error probability expression for the AWGN channel in the form P_e≈Q(√(1.1716·E_b/N₀)) where Q(·) is the Gaussian distribution Q-function and E_b /N₀ is the bit energy-to-noise density ratio. Exact BER expressions for the Rayleigh-fading channel that involve the noise parameters are also given and are extended to the case of L-fold diversity combining     

0.25-μm gate millimeter-wave ion-implanted GaAs MESFETs

Quarter-micrometer gated ion-implanted GaAs MESFETs which demonstrate device performance comparable to AlGaAs/InGaAs pseudomorphic HEMTs (high-electron mobility transistors) have been successfully fabricated on 3-in-diameter GaAs substrates. The MESFETs show a peak extrinsic transconductance of 480 mS/mm with a high channel current of 720 mA/mm. From S-parameter measurements, the MESFETs show a peak current-gain cutoff frequency f_t of 68 GHz with an average f_t of 62 GHz across the wafer. The 0.25-μm gate MESFETs also exhibit a maximum-available-gain cutoff frequency f_t greater than 100 GHz. These results are the first demonstration of potential volume production of high-performance ion-implanted MESFETs for millimeter-wave application     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

On the speed and noise performance of direct ion-implanted GaAsMESFETs

Recent advances in high-speed and ultra-low-noise performance of GaAs MESFETs are reviewed. Experimental results showing that the current gain cutoff frequency and noise figure achieved by direct ion-implanted GaAs MESFETs are equal to or better than those achieved by GaAs HEMTs are presented. Detailed cryogenic-temperature microwave measurements of F_t on HEMTs and MESFETs are reported, showing a similar dependence of the effective velocity with temperature. It is concluded that the transport properties of the high electron mobility in the two-dimensional electron gas in HEMTs have been misinterpreted for high-speed device operation, and that the high-field velocity is the most important parameter for high-speed device operation. It is the fundamental Γ-L valley separation of the material and the associated effectiveness, either GaAs or InGaAs, that limit the high-field velocity and thus the speed of the devices     

50-nm T-Gate InAlAs/InGaAs Metamorphic HEMTs With Low Noise and High fT Characteristics

We report 50-nm T-gate metamorphic high-electron mobility transistors (MHEMTs) with low noise figure and high characteristics. The 30 mumtimes2 MHEMT shows a drain current density of 690 mA/mm, a g_m,max of 1270 mS/mm, an f_T of 489 GHz, and an of 422 GHz. In the frequency range of 59-61 GHz, the noise figure is less than 0.7 dB, and the associated gain was greater than 9 dB at a drain voltage of 1.3 V and a gate voltage of -0.8 V. To our knowledge, the MHEMT shows the best performance in terms of and noise figure among GaAs-based HEMTs.