ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC). Current field-programmable gate arrays (FPGAs) have over million lookup tables, making it possible to prototype a complete NoC-based MCSoC on a single FPGA device. FPGA prototyping allows rapid system verification and optimum design parameters estimation. However, existing NoC-based MCSoC prototypes are usually adopting simple NoC architectural functionality. These NoC prototypes cannot represent a realistic projection of the state-of-the-art application-specific integrated circuit (ASIC) NoCs as these prototypes have limited overall system performance. This paper presents ProNoC, an integrated tool for rapid prototyping and validation of NoC-based MCSoC projects targeting FPGA devices. ProNoC adopts most advanced NoC features such as the support of virtual channel (VC), virtual network, low latency routing and different routing algorithms. Results show that NoC interconnect in ProNoC outperforms CONNECT, the most recent VC based prototype NoC with lower logic cell utilization, higher maximum operating frequency, higher average saturation throughput, and lower average communication latency. Moreover, ProNoC is equipped with graphical user interface to facilitate the development of MCSoC prototypes on FPGA platforms.     

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

The simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of state-of-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simulation models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.     

权衡能耗与延迟的数据融合算法研究

在无线传感器网络的路由协议中考虑数据融合能极大地提高网络生存期性能,但随之会带来网络可靠性下降、数据传输延迟增加等问题。设计一种新的可权衡能耗与延迟的数据融合算法ECLT,通过二级模糊综合评判的方式来调整原有的路由信息,增加数据传输路径间的交叠,以提高数据融合度、延长网络生存期;同时,传感节点在转发数据的过程中还可根据本身状态来动态调整进行数据融合的等待时间,从而在均衡网络中各节点能耗的同时减少了数据传输延迟。经仿真验证,该算法能在极大的延长无线传感器网络使用寿命的同时降低数据的平均传输延迟。     

Distributed topology discovery in self-assembled nano network-on-chip

In this paper, we present DiSR, a distributed approach to topology discovery and defect mapping in a self-assembled nano network-on-chip. The main aim is to achieve the already-proven properties of segment-based deadlock freedom requiring neither a topology graph as input, nor a centralized algorithm to configure network paths. After introducing the conceptual elements and the execution model of DiSR, we show how the open-source Nanoxim platform has been used to evaluate the proposed approach in the process of discovering irregular network topology while establishing network segments. Comparison against a tree-based approach shows how DiSR still preserves some important properties (coverage, defect tolerance, scalability) while avoiding resource hungry solutions such as virtual channels and hardware redundancy. Finally, we propose a gate-level hardware implementation of the required control logic and storage for DiSR, demonstrating a relatively acceptable impact ranging from 10 to about 20% of the budget of transistors available for each node.     

ARM7TDMI power consumption

Portable and handheld products require processors that consume less power than those in desktop and other powered applications. As a result, designers must analyze power use in the early stage of design both at the circuit and system levels. RISC processors, such as our ARM7TDMI, have both strengths and weaknesses as far as power consumption is concerned. From a system perspective, RISC processors should consume more power than CISC processors since RISCs need to be fed with an instruction virtually every cycle. RISC processors usually have a fixed 32bit instruction format, which forces a 32-bit memory access every cycle. Thus, the processor consumes power both in accessing the memory and in driving 32 address and 32 data wires across a PCB     

多移动汇聚节点的无线传感网中基于服务质量的能耗

针对无线传感网（WSN）中传感节点能耗过高、传输时延过长、数据完整性过差的问题,提出一种基于多移动汇聚节点考虑服务质量（QoS）的路由算法——时延敏感和数据完整性（MSTSDI）算法。首先,通过从基站接收信号的强度判断节点的密度,用K-means聚类算法将传感网划分成自治区域;其次,给每个自治区域分配一个移动汇聚节点,利用支持向量回归（SVR）的方法确定移动汇聚节点的轨迹;最后,引入深度引力域和队列引力域,通过Improved-IDDR算法对时延敏感数据包和数据完整性要求高的数据包进行传输。理论分析和仿真表明,与GLRM算法和LEACH算法相比,Improved-IDDR算法的路由策略的能耗下降幅度分别为21.2%和23.7%;而该算法的时延分别降低了15.23%和17.93%;该算法的所传输数据包的完整性也更好。实验结果表明,MSTSDI在传感网络中能够有效提高系统的性能。     

片上网络映射优化问题研究与进展

映射优化问题是片上网络关键技术之一,其模型的建立及求解影响着片上网络性能。映射问题被证明是NP问题,传统求解具有一定的难度,多采用启发式算法完成。为了解当前映射优化问题研究现状及发展前景,针对片上网络IP核到网络节点的匹配优化问题进行建模和分类,并对当前研究中的一些典型映射算法在目标、约束条件、性能、采用拓扑结构等方面进行对比分析,最后给出片上网络中映射优化问题未来的研究方向。     

Multi-objective optimal reactive power dispatch considering voltage stability in power systems using HFMOEA

This paper proposes a new hybrid fuzzy multi-objective evolutionary algorithm (HFMOEA) based approach for solving complex multi-objective, mixed integer nonlinear problems such as optimal reactive power dispatch considering voltage stability (ORPD-VS). In HFMOEA based optimization approach, the two parameters like crossover probability (P_C) and mutation probability (P_M) are varied dynamically through the output of a fuzzy logic controller. The fuzzy logic controller is designed on the basis of expert knowledge to enhance the overall stochastic search capability for generating better pareto-optimal solution. Two detailed case studies are presented: Firstly, the performance of HFMOEA is tested on five benchmark test problems such as ZDT1, ZDT2, ZDT3, ZDT4 and ZDT6 as suggested by Zitzler, Deb and Thiele; Secondly, HFMOEA is applied to multi-objective ORPD-VS problem. In both the case studies, the optimization results obtained from HFMOEA are analysed and compared with the same obtained from two versions of elitist non-dominated sorting genetic algorithms such as NSGA-II and MNSGA-II in terms of various performance metrics. The simulation results are promising and confirm the ability of HFMOEA for generating better pareto-optimal fronts with superior convergence and diversity.     

一种低功耗的旋进漩涡流量计

为使旋进漩涡流量计扩大应用场合、适用于电池供电,设计了一种低功耗的外电供电与电池供电自动切换的旋进漩涡流量计,重点分析了硬件上的主控芯片MSP430F4794、电源管理模块、温度压力采样模块、铁电存储模块与软件上的温度压力定时采样和M C U进入低功耗模式的降低功耗设计。实验测试结果证明,该设计大大降低了旋进漩涡流量计电池供电时的整机功耗,同时保证了流量脉冲采集与脉冲输出的较高精度。     

Reducing disk power consumption in servers with DRPM

Although effective techniques exist for tackling disk power for laptops and workstations, applying them in a server environment presents a considerable challenge, especially under stringent performance requirements. Using a dynamic rotations per minute approach to speed control in server disk arrays can provide significant savings in I/O system power consumption without lessening performance.     

三维片上网络正四面体裂变拓扑结构研究

旨在研究新型三维片上网络正四面体裂变拓扑结构,给出了该拓扑结构的生成过程;对该拓扑结构进行了编码设计和路由设计。通过对gpNoCsim片上网络仿真器进行三维扩展,对正四面体裂变拓扑结构进行性能仿真实验。仿真结果表明,在均匀负载模式下,正四面体裂变拓扑结构的平均延时和平均跳数均低于Mesh结构,当注入率为0.02时,平均延时比Mesh结构低16.8%、平均跳数比Mesh结构少5.5%;在局部负载模式下,当注入率大于0.008时,正四面体裂变拓扑结构的平均延时和平均跳数与Mesh结构相比,均有明显改善;当注入率为0.014时,平均延时比 Mesh结构降低18.7%、平均跳数比 Mesh结构减少9.6%。说明正四面体裂变拓扑结构可用于三维片上网络拓扑结构设计。     

A coordinated dispatch method for energy storage power system considering wind power ramp event

In response to the impact of wind power ramp events on power system, a forecast and coordinated dispatch method for wind power ramp events is proposed. Firstly, the LSTM neural network is utilized to multi-step forecast the wind power, which can identify the features such as amplitude and duration of wind power ramp event in advance. Then, an ahead-delay adjustment method (ADAM) for wind power ramp events is proposed, which coordinates the thermal power generation units (referred to as units) and the energy storage system (referred to as ESS) to make two-step adjustments during the period before and after wind power ramp event. Thereby reducing the ramp rate of wind power, while reducing the requirement for the output power and capacity of ESS. Based on the above methods, a coordinated dispatch model of units and ESS considering wind power ramp events is established. The units are coordinated in advance to ensure sufficient adjustable reserves during wind power ramp events. A more economical and reliable dispatch plan can be achieved by coordinating the units and ESS according to the judging conditions. Finally, the forecast performance test and the ramp dispatch simulation are carried out in case study to verify the effectiveness of the forecast and dispatch method.     

射频唤醒技术在WSNs低功耗中的应用

针对WSNs节点功耗较高,电池供电寿命短等缺点,提出了考虑多项参数的倍压整流电路分析模型,并利用该模型设计了具有限幅功能的低功耗唤醒电路。该模型的稳态响应不但与仿真结果相吻合,而且在实际输入信号频率为915MHz,功率为10dBm时,能正确解调出发射端设定的序列,距离较近时,限制幅值在2．3V左右,并且该模块具有长达22m唤醒距离,大大降低了节点功耗,产生直接的经济效益。     

Modelling and optimization of power consumption in wireless access networks

The power consumption of wireless access networks will become an important issue in the coming years. In this paper, the power consumption of base stations for mobile WiMAX, fixed WiMAX, UMTS, HSPA, and LTE is modelled and related to the coverage. A new metric, the power consumption per covered area PC_area, is introduced, to compare the energy efficiency of the considered technologies for a range of bit rates. Assuming the model parameters are correct, the conclusions are then as follows. For a 5 MHz channel, UMTS is the most energy-efficient technology until a bit rate of 2.8 Mbps, LTE between 2.8 Mbps and 8.2 Mbps, fixed WiMAX between 8.2 Mbps and 13.8 Mbps and finally mobile WiMAX for bit rates higher than 13.8 Mbps. Furthermore, the influence of MIMO is investigated.For a 2 × 2 MIMO system, PC_area decreases by 36% for mobile WiMAX and by 23% for HSPA and LTE compared to the SISO system, resulting in a higher energy efficiency.The power consumption model for base stations is used in the deployment tool GRAND (Green Radio Access Network Design) for green wireless access networks. GRAND uses a genetic based algorithm and is applied on an actual case for the Brussels Capital Region, showing the possibilities of energy-efficient planning.     

Minimum of power consumption in the problem of oscillation damping

Consideration was given to minimization of the L ¹-norm of control of the linear oscillatory system. For consumption of the energy resources required to damp oscillations, bilateral estimates were obtained.     

New 802.11h mechanisms can reduce power consumption

The original purpose of the IEEE 802.11h standard was to extend WLAN operation in Europe to the 5 GHz band, where WLAN devices need dynamic frequency selection (DFS) and transmit power control (TPC) to coexist with the band's primary users, i.e. radar and satellite systems. Although 802.11h defines the mechanisms or protocols for DFS and TPC, it does not cover the implementations themselves. With some amendments to the 802.11h standard to address this need, the mechanisms for DFS and TPC can be used for many other applications with the benefits of automatic frequency planning, power consumption reduction, range control, interference reduction, and quality-of-service enhancement. MiSer is presented as a simple application example for saving significant communication energy for 802.11h devices.     

Look-ahead architecture adaptation to reduce processor power consumption

An effective approach to reducing processor power consumption is to adaptively activate and deactivate hardware resources. The authors propose a look-ahead scheme that adjusts the processor issue rate triggered by main-memory accesses. This architecture-independent technique is particularly effective for memory-intensive applications. Combined with an existing technique based on IPC values, it also reduces power consumption for computation-intensive applications.