Efficient designs of reversible sequential circuits

The Journal of Supercomputing - Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and...     

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD–ES, which combines the 3SD method with the (μ, λ) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD–ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.     

A design method for nanofluidic circuits

A design method is proposed for nanofluidic circuits, based on the flow equation for a nanoscale fluid flow. This method incorporates the use of the concepts of the flow resistance, the flow rate, the pressure drop and the power loss, as like in electric circuits. The equations for calculating the flow resistance and the power loss in exemplary nanofluidic circuits including in a nanotube tree are presented. It was found that the nanotube size and the fluid-tube wall interaction both have great influences on the flow resistance and the power loss in nanochannel flow. Exemplary design analysis is given for some nanofluidic circuits, based on the proposed method.

     

Minimal universal library for reversible circuits

Reversible logic plays an important role in quantum computing. Several papers have been recently published on universality of sets of reversible gates. However, a fundamental unsolved problem remains: “what is the minimum set of gates that are universal for n-qubit circuits without ancillae bits”. We present a library of 2 gates which is sufficient to realize all reversible circuits of n variables. It is a minimal library of gates for binary reversible logic circuits. We also analyze the complexity of the syntheses.     

A test-pattern-generation algorithm for sequential circuits

A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for deterministic automatic test pattern generation (ATPG). Essential is based on the well-known method of reverse time processing, but it applies forward processing within time frames to avoid disadvantageous a priori determination of a path to be sensitized or of a primary output to which the fault effects must be propagated. It is designed to exploit fully the sophisticated techniques used for combinational circuits in the Socrates ATPG system. Experimental results for sequential ATPG obtained with Essential (implemented in C on a Sequent Symmetry computer) are reported     

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.     

A module-level three-stage approach to the evolutionary design of sequential logic circuits

In this study, we propose a module-level three-stage approach (TSA) to optimize the evolutionary design for synchronous sequential circuits. TSA has a three stages process, involving a genetic algorithm (GA), a pre-evolution, and a re-evolution. In the first stage, the GA simplifies the number of states and automatically searches the state assignment that can produce the circuit with small complexity. Then, the second stage evolves a set of high-performing circuits to acquire frequently evolved blocks, which will be re-used for more compact and simple solutions in the next stage. In this stage, a genetic programming (GP) is proposed for evolving the high-performing circuits and data mining is used as a finder of frequently evolved blocks in these circuits. In the final stage, the acquired blocks are encapsulated into the function and terminal set to produce a new population in the re-evolution. The blocks are expected to make the convergence faster and hence efficiently reduce the complexity of the evolved circuits. Seven problems of three types—sequence detectors, modulo-n counters and ISCAS89 circuits—are used to test our three-stage approach. The simulation results for these experiments are promising, and our approach is shown to be better than the other methods for sequential logic circuits design in terms of convergence time, success rate, and maximum fitness improvement across generations.     

The Methodology of Testability Prediction for Sequential Circuits

Increasingly,test generation algorithms are being developed with the continuous creations of incredibly sophisticated computing systems.Of all the developments of testable as well as reliable designs for computing systems,the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue.Although dozens of algorithms have been proposed to cope with this issue,it still remains much to be desired in solving such problems as to determin 1) which of the existing test generation algorithms could be the most efficient for some particular circuits(by efficiency,we mean the Fault Coverage the algorithm offers,CPU time when executing,the number of test patterns to be applied,ectc.)since different algorithms would be preferable for different circuits;2)which parameters(such as the number of gates,flip-flops and loops,etc., in the circuit)will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.Testability forecastin methodology for the sequential circuits using regression models is presented which a user usually needs for analyzing his own circuits and selecting the most suitable test generation algorithm from all possible algorithms available.Some examples and experiment results are also provided in order to show how helpful and practical the method is.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

A comprehensive fault diagnosis technique for reversible logic circuits

Fault diagnosis is a complex and challenging problem in reversible logic circuits. The paper proposes a novel fault diagnosis technique for missing control faults in reversible logic circuits. The main focus of this technique is to extract the unique fault signature for each missing control fault in the circuit. The fault signatures are the sequences of test vectors to identify the location of the faults. Based on these fault signatures a unique fault diagnosis tree is built. Our proposed fault diagnosis algorithm is used to traverse the fault diagnosis tree to find the presence and location of the fault. The traversal process is simple and fast. The algorithm executes in linear time and experimental results for benchmark circuits show the reduction of test patterns compared to earlier works.     

Upper bounds for reversible circuits based on Young subgroups

We present tighter upper bounds on the number of Toffoli gates needed in reversible circuits. Both multiple controlled Toffoli gates and mixed polarity Toffoli gates have been considered for this purpose. The calculation of the bounds is based on a synthesis approach based on Young subgroups that results in circuits using a more generalized gate library. Starting from an upper bound for this library we derive new bounds which improve the existing bound by around 77%.     

An approximate sequential optimization and reliability assessment method for reliability-based design optimization

Sequential optimization and reliability assessment (SORA) is one of the most popular decoupled approaches to solve reliability-based design optimization (RBDO) problem because of its efficiency and robustness. In SORA, the double loop structure is decoupled through a serial of cycles of deterministic optimization and reliability assessment. In each cycle, the deterministic optimization and reliability assessment are performed sequentially and the boundaries of violated constraints are shifted to the feasible direction according to the reliability information obtained in the previous cycle. In this paper, based on the concept of SORA, approximate most probable target point (MPTP) and approximate probabilistic performance measure (PPM) are adopted in reliability assessment. In each cycle, the approximate MPTP needs to be reserved, which will be used to obtain new approximate MPTP in the next cycle. There is no need to evaluate the performance function in the deterministic optimization since the approximate PPM and its sensitivity are used to formulate the linear Taylor expansion of the constraint function. One example is used to illustrate that the approximate MPTP will approach the accurate MPTP with the iteration. The design variables and the approximate MPTP converge simultaneously. Numerical results of several examples indicate the proposed method is robust and more efficient than SORA and other common RBDO methods.     

Saving power by synthesizing gated clocks for sequential circuits

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area     

Line ordering of reversible circuits for linear nearest neighbor realization

Real quantum computing technologies have different restrictions and constraints which need to be considered during circuit synthesis. In certain technologies, only physically adjacent qubits can interact, which restricts their realizations to only linear nearest neighbor (LNN) architecture. In this work, we formulate the line ordering problem in LNN architecture as task assignment problem to find a mapping (permutation) between task graph and processor graph with minimum cost. We propose two different approaches, a greedy heuristic and a meta-heuristic algorithm based on Harmony Search to solve the task assignment problem. Experimental results show that our algorithms were able to reduce the quantum cost of benchmark circuits by approximately 30 % on average. Moreover, the proposed algorithms were compared to one recently proposed ordering algorithm and were found to further improve the cost by approximately 16 %.     

Synthesis of reversible circuits with minimal costs

We present fast algorithms to synthesize exact minimal reversible circuits for various types of gate and cost. By reducing reversible logic synthesis problems to permutation group problems, we use the powerful algebraic software GAP to solve such problems. Our approach can minimize for arbitrary cost functions of gates. In addition, we show that Peres gates are a better choice than the standard Toffoli gates in libraries of universal reversible gates. This work was supported by the NNSF of China under Grant 60773205 and the Fund of Cultivating Leading Scholars in UESTC.     

Low-cost environment for analysis and design of knowledge-based control algorithms

A dedicated low-cost environment for analysis and design of knowledge-based control systems of continuous-time processes HEXOON is described. It is implemented on IBM PC/AT compatible computers under MS-DOS and includes three main parts — a special real-time operating system shell (RTOSS), a medium scale expert system shell (ESS) and a simulation program named RSOOPE. The so-called “progressive reasoning” mechanism is in the base of the ESS in order to improve the speed of reasoning and ensure a proper control signal at each sample time for various control system structures. HEXOON supplies the user with facilities to analize a system working in two modes — direct control and simulation. Thus it is very useful for education of students and training of control engineers in the field of intelligent control.