基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括 /-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.     

金属纳米晶存储器件数据保持能力建模与验证

金属纳米晶存储器件具有低功耗、高速读写特性及较高的可靠性,因此近年来在非易失存储器研究领域备受关注.对比分析讨论了量子限制效应与库仑阻塞效应对金属纳米晶费密能级的影响后,发现库仑阻塞效应会严重削弱器件数据保持能力.在综合考虑金属纳米晶量子限制效应和库仑阻塞效应的基础上,提出了金属纳米晶存储器件数据保持能力分析模型,并通过与相关研究文献的实验数据对比分析,证实了本模型的合理性.     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

基于PVK/PbS纳米晶有机无机复合薄膜电双稳器件性能研究

通过简单旋涂方法,制备了一种基于硫化铅（PbS）纳米晶与聚乙烯基咔唑（PVK）的有机/无机复合薄膜电双稳器件,并对所制备的器件进行性能测试及其电荷传输机制研究。首先采用热注入的方法制备了尺寸均一的立方形PbS纳米晶,然后将PbS纳米晶与PVK聚合物混合作为活性层材料,制备了有机/无机复合薄膜电双稳器件。该器件展示了良好的电双稳特性并且可以实现稳定的“读-写-读-擦”操作。器件的最大电流开关比能够达到10⁴。并进一步对器件在正向电压下的I-V曲线进行了理论拟合,发现在不同电流传导状态下,器件符合不同的电传导模型。进而分析了该电双稳器件中的电荷传输机制,认为在电场的作用下,发生在纳米晶与聚合物之间的电场诱导电荷转移是产生电双稳特性的主要原因。     

利用同步晶化法制备的镍纳米晶的电荷存储特性

快速退火纳米晶化法是目前常用的金属纳米晶制备方法,但其后续600~900℃高温退火会降低器件的电学特性和可靠性。本文提出了热预算低的金属纳米晶制备的新方法—沉积过程中的同步金属薄膜原位纳米晶化法,可以省掉后续单独的退火处理工艺,使金属薄膜同步产生纳米晶化,降低工艺热功耗及简化工艺,从而有效地改善上述薄膜沉积后退火纳米晶化法的不足。在不同衬底温度（250~325 ?C）下,利用同步纳米晶化法制备镍纳米晶存储器。随着生长温度的增加,其存储窗口先增加到最大值再降低。衬底温度为300 ?C时,其存储窗口（2.78 V）最大。与快速热退火法镍纳米晶存储器相比较,同步纳米晶化法制备镍纳米晶存储器具有更强的电荷存储能力。另外,研究了不同操作电压和脉冲时间下器件的平带电压偏移量,当操作电压增加到±10 V时出现了较大的平带电压偏移量,这表明器件发生了大量的载流子（电子和空穴）注入现象。最后,模拟了金属纳米晶存储器的载流子（电子和空穴）注入和释放过程。     

硅纳米晶存储器的耐受性研究

首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。     

沟道应力对纳米尺度MOSFET器件特性的影响

利用ISE DESSIS器件模拟工具,模拟了纳米尺度的MOSFETs器件沟道中存在应力时的器件特性,分析了应力大小和方向发生变化对MOSFET的阈值电压、亚阈特性等器件特性的影响.     

纳米级自开关二极管的电学特性研究

纳米级自开关二极管是一种通过破坏器件表面对称性来实现整流特性的纳米级新型晶体管.首先通过建立In0.53Ga0.47As/In0.52Al0.48As纳米级自开关二极管的二维器件模型,采用蒙特卡罗方法,模拟了自开关器件的电子输运特性,根据该器件模型研究了在不同几何结构参数条件下的自开关器件的电学特性,并对影响器件电学特性的结构参数进行了仿真分析.结果表明,器件的Ⅰ-Ⅴ特性强烈地受到导电沟道宽度、沟槽宽度、沟道长度和表面态密度的影响,通过优化器件的结构参数可使器件获得更优越的整流特性.     

沟道应力对纳米尺度MOSFET器件特性的影响

利用ISE DESSIS器件模拟工具,模拟了纳米尺度的MOSFETs器件沟道中存在应力时的器件特性,分析了应力大小和方向发生变化对MOSFET的阈值电压、亚阈特性等器件特性的影响.     

沟道应力对纳米尺度MOSFET器件特性的影响

利用ISE DESSIS器件模拟工具，模拟了纳米尺度的MOSFETs器件沟道中存在应力时的器件特性，分析了应力大小和方向发生变化对MOSFET的阈值电压、亚阈特性等器件特性的影响.     

Hysteresis in transfer characteristics in 4H-SiCdepletion/accumulation-mode MOSFETs

Hysteresis in room-temperature transfer characteristics between forward (pinch-off voltage, V_P=-15 V) and reverse gate voltage sweeps (V_P=7 V) in n-channel depletion/accumulation-mode 4H-SiC MOSFETs is reported. Transfer characteristics exhibit a parallel shift toward negative voltages depending,on the starting gate voltage and direction of the sweep. The hysteresis and shift in transfer characteristics are related to changes in effective fixed-oxide charge resulting from changes in interface trap occupancy. Interface trap occupancy changes depending on the magnitude of the starting gate voltage and the direction of gate-voltage sweep. At high temperatures, the hysteresis between forward and reverse gate voltage sweep decreases     

Temperature and voltage aging effects on electrical conduction mechanism in epoxy-BaTiO3 composite dielectric used in embedded capacitors

The electrical conduction mechanism in an embedded capacitor with epoxy-BaTiO₃ composite dielectric and Cu electrodes is investigated in this paper. Leakage current was measured across the dielectric by performing a voltage sweep from 0 to 100 V. The voltage sweep was performed at temperatures ranging from 25 °C to 125 °C. Various electrical conduction models such as Schottky, Poole-Frenkel, and ionic hopping were evaluated by comparing the functional dependence of leakage current on temperature and voltage for each mechanism which was considered. It was observed that the conduction mechanism was most consistent with Schottky emission. The contact potential barrier corresponding to Schottky emission was found to be 1.29 eV.The effect of combined temperature and voltage aging on the conduction mechanism was investigated by aging the embedded capacitor dielectric at 125 °C and 100 V for 1680 h. To investigate the difference between combined temperature and voltage aging and temperature aging alone, some capacitors were aged only by temperature at 125 °C for 1680 h. Measurements of leakage current as a function of temperature and voltage were performed at frequent intervals during the aging. It was observed that the value of leakage current did not increase during temperature and voltage aging unlike pure BaTiO₃ dielectrics.     

Effect of temperature and voltage sweep rate on C ƒ- V characteristics of MIS capacitors

The capacitance (C) vs voltage (V) characteristics of metal-insulator-semiconductor (MIS) capacitors have been measured, with temperature and sweep rate as parametric variables. The steady-state portions of the curves are seen to be strongly temperature dependent, while the non-steady-state portion of the curves exhibit pronounced hysteresis. The striking features of this portion of the curves is that the amount of hysteresis is only slightly dependent on temperature and sweep rate. Generally speaking, the curves are in good agreement with theoretical predictions.At relatively high temperature and high sweep rates, the non-steady-state portion of the C?V curve exhibits a minimum on the negative-going voltage cycle (for devices with n-type substrates). This phemenon is explained in terms of the combined effects of surface and bulk generation in the semiconductor. During the non-steady-state positive-going voltage cycle the C?V characteristic overshoots the steady-state inversion C ? V characteristic. This is explained in terms of the necessity of having the Fermi level of the semiconductor slightly above the level of the uppermost-filled trap, in order that there will be a net flow of current into the interface traps.     

A new wafer level reliability method for evaluation of ionic induced pmosfet drift effects

An ionic induced pMOSFET drift effect was investigated by deliberately enhancing the sodium concentration in interlevel dielectric layers.High frequency capacitance voltage and triangular voltage sweep (TVS) measurements as well as different bias temperature stress sequences were employed to show that the degradation is a two step process: sodium drift into active areas and charging of traps which were generated by sodium interactions with the semiconductor oxide interface.A special wafer level reliability method was developed which takes into consideration the two phase nature of the failure mechanism.     

Experimental response of MOS devices to a fast linear voltage ramp

An experimental investigation is undertaken of the response of an MOS device to a linear voltage ramp of such speed as to take the device into non-equilibrium, but to allow sufficient generation to take place during the voltage sweep to provide structure in the C-V curves which can be analysed quantitatively. The main aim has been to investigate the effect of sweep rate per se, but additional data is presented which considers the voltage dependence of the space-charge width, the maximum sweep rate for quasi-equilibrium, and the effect of temperature. It is demonstrated that the technique provides quantitative information on bulk traps and a qualitative measure of the relative role of interface traps in the generation process. Transitions are observed between quasi-equilibrium and non-equilibrium which are a function of sweep rate. This is in contrast to the pulse technique, where the response is of a purely transient nature.     

Nonlinear characterization of GaN HEMT

DC I-V output, small signal and an extensive large signal characterization (load-pull measurements) of a GaN HEMT on a SiC substrate with different gate widths of 100μm and 1 mm have been carried out. From the small signal data, it has been found that the cutoff frequencies increase with gate width varying from 100μm to 1 mm, owing to the reduced contribution of the parasitic effect. The devices investigated with different gate widths are enough to work in the C band and X band. The large signal measurements include the load-pull measurements and power sweep measurements at the C band (5.5 GHz) and X band (8 GHz). When biasing the gate voltage in class AB and selecting the source impedance, the optimum load impedances seen from the device for output power and PAE were localized in the load-pull map. The results of a power sweep at an 8 GHz biased various drain voltage demonstrate that a GaN HEMT on a SiC substrate has good thermal conductivity and a high breakdown voltage, and the CW power density of 10.16 W/mm was obtained. From the results of the power sweep measurement at 5.5 GHz with different gate widths, the actual scaling rules and heat effect on the large periphery device were analyzed, although the effects are not serious.The measurement results and analyses prove that a GaN HEMT on a SiC substrate is an ideal candidate for high-power amplifier design.     

Bias Voltage Controlled Memory Effect in In-Plane Quantum-Wire Transistors With Embedded Quantum Dots

The drain-current through GaAs/AlGaAs quantum-wire transistors (QWTs) with InGaAs quantum dots (QDs) exploited as floating gates is studied for temperatures up to 150 K. It is found that the threshold hysteresis between the up sweep and the down sweep of the gate voltage decreases with increasing bias voltage and is suppressed at a critical bias voltage. It is proposed and demonstrated that these QWTs show logic OR-gate functionality with the option to store the corresponding logic state by switching the bias voltage to zero. The authors explain this behavior by a bias voltage dependent efficiency of the gate to control differently the QDs and the quantum wire     

基于压电陶瓷的风机叶片模型覆冰主动监测

南方山区高湿低温严酷环境易导致冰灾,风机叶片覆冰会导致发电效率降低甚至停机,因此发展高效可靠的风机叶片覆冰监测技术对防冰、除冰具有重要意义。该文提出了一种基于压电陶瓷应力波测量的风机叶片覆冰主动监测方法。开展叶片模型进行模拟覆冰试验,在叶片表面布置伸缩型和剪切型两种压电陶瓷片,根据波动法原理对驱动器输入正弦扫频电压信号作为激励,记录不同传感器在不同结冰厚度下的响应信号,并对测量信号进行小波包能量分析。结果表明,同一压电陶瓷片接收信号的小波包能量与结冰厚度存在明显关系。     

A precision monolithic time delay generator for use in automotive electronic fuel injection systems

A high-performance low-cost IC time-delay generator has been developed to be used as a building block for automotive electronic fuel injection systems. Time-delay accuracies are achieved by employing the IC to precisely control both the reset time and the initial ramp voltage of an external RC voltage sweep circuit by means of a gated voltage regulator. Reference information, derived from the rotating distributor shaft, triggers an input flip-flop that controls a reset generator to produce the required gating pulses. The resulting exponential voltage sweep is sensed at the input of three externally programmable voltage comparators that provide three separate time-delayed output signals within a /spl plusmn/1-percent accuracy from -40/spl deg/ to +125/spl deg/C. This technique is contrasted to a linear voltage sweep approach which offers less desensitivity to IC parameter variations.