基于CUDA平台的数据库序列比对算法加速

在生物信息学中,数据库序列比对是极为常用的操作,Smith-Waterman算法是最流行的序列比对算法,精确度高,但是计算复杂度高,在进行大量的序列比对非常耗时。另外,生物技术的发展使得已知的序列数据库变得越来越庞大,这导致进行数据库序列比对所消耗的时间也越来越长,因而有必要加速数据库序列比对算法。NVIDIA提出了CUDA编程架构,相比之前的GPGPU具有更好的可编程性,用户可以更轻松地发掘出GPU强大的计算能力。在CUDA平台上实现了Smith-Waterman的数据库序列比对算法的并行加速,速度优于已有的基于GPU的实现,超过了基于启发式算法的BLAST算法执行速度。     

基于FPGA的IDEA加解密算法的研究和实现

加密技术是数据保密通信的关键技术。研究加密算法、保障数据安全具有重要的现实意义。IDEA算法是一个好的加解密算法。本文用FPGA设计并实现了IDEA算法的加解密器。对于算法实现的关键运算模块,通过对几个经典运算算法的比较验证,选择合适的算法进行优化设计。利用状态机的优良特性控制算法的运算。结果表明,该设计消耗资源少,运算速度快,算法更适应FPGA特性,具有一定的应用价值。     

基于FPGA的罗兰C前端IIR数字带通滤波器设计

针对罗兰C前端带通滤波的需求,提出了采用级联形式在FPGA上实现罗兰C数字带通滤波器的方法。首先利用Matlab设计出满足要求的滤波器,考虑硬件设计要求将参数进行取整,并对取整前后的滤波效果进行了比对分析。在硬件程序设计前在Matlab下用级联式差分方程模拟硬件滤波算法,以提高设计的成功率。最后在FPGA下用Veril...     

字符串匹配算法的实现:CPU vs.GPU vs.FPGA

针对字符串匹配算法在各平台实现的性能问题,将算法在CPU、GPU及FPGA上做了测试对比。GPU具有计算单元多的特点,使得GPU对计算密集型应用有较大的效率提升;而FPGA具有级强的灵活性、可编程性及大量的逻辑运算单元,在处理字符串匹配时的处理速度快。通过对3种实现方式在Snort规则库下做的分析,其结果表明,FPGA的处理速度最快,相比GPU的处理速度提升了10倍。而CPU的串行处理速度最慢,且FPGA的资源消耗最多,GPU次之,CPU的资源消耗最少,且实现最简单。     

利用CUDA加速连续波雷达测速算法

针对连续波雷达中事后分析系统的运算数据量大,运算时间长的特点,提出了一种利用CUDA平台的GPU进行加速运算的方法,它利用GPU的并行运算功能来完成FFT算法。实验结果表明,相比以往用CPU进行事后分析,利用CUDA平台进行事后分析的速度有明显提升。     

基于FPGA的数字混沌序列的实现及性能分析

为了产生数字混沌PN序列,提出了一种基于FPGA平台的连续混沌数字化技术.针对一个混沌系统,利用理论和 数值仿真对系统的基本特性进行了分析,通过Lyapunov指数谱和分叉图对系统的状态转换进行了分析.在Matlab的Simulink 下,利用DSPBuilder设计了一个电路,并转换成VHDL代码程序,用Quartu...     

利用状态数据的无人平台测控协议逆向分析方法

针对无人平台测控数据通信安全问题,提出了一种测控协议逆向分析模型.模型采用数据挖掘方法对通信报文中的协议格式和语义信息进行分析,主要采用改进BF(Brute-Force)算法和AP(Affinity-Propagation)算法进行模式串匹配和关联规则提取,以提取协议初步格式;采用序列比对技术中改进SW(Smith-Waterman)算法,结合监测状态数据对格式和语义信息作进一步分析.通过仿真实验模拟协议逆向分析了所需要的无人平台与基站的通信数据和雷达监测状态数据;根据协议逆向模型仿真试验结果可得到100%的协议格式识别率和90.9%的语义识别率,结果证明了提出的逆向分析模型的有效性.     

OFDM系统中基于PN的信道估计算法及FPGA设计

根据伪随机噪声（PN）序列的相关特性，介绍一种OFDM系统中在时域利用PN序列的循环相关对信道进行估计的算法，并利用周期序列的循环卷积特性对接收数据进行频域均衡。最后列出其FPGA设计流程和仿真图形。     

基于正弦反馈Logistic混沌映射的图像加密算法及其FPGA实现

基于混沌的数字图像加密算法因具有较大的密钥空间和较高的密钥敏感特性等而被广泛地应用。该文在经典Logistic映射中引入正弦反馈,构成新的映射关系,并分析该映射的混沌行为。利用混沌映射导出离散混沌加密序列,并对加密序列进行放大取整,增强其伪随机性;利用NIST随机性测试方法测试了加密序列的伪随机性;将伪随机序列与原始图像进行异或运算,实现图像加密。数值仿真结果表明所提加密算法具有较好的加密效果,其密钥也具有较好的敏感性和伪随机性,最后基于FPGA平台的硬件加密实现了本算法。     

基于FPGA的背光图像校正系统设计

文章结合了OTSU算法和多尺度Retinex算法,在FPGA平台上设计完成了一个实时的背光图像处理系统。Retinex算法是一种广泛使用的图像增强的算法,但是受限于其复杂的运算在硬件上却没有得到很好推广。文章利用查表法和流水线的方法解决多尺度Retinex算法中的复杂运算,使其适合在FPGA上运行。Retinex算法处理的图像会存在局部增强过度颜色失真的问题,针对这一问题文章采用OTSU算法将图像分割,然后对亮部和暗部分别处理,最后再对处理后的结果融合。     

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D–Stacked Architecture

Rapidly developing Next Generation Sequencing technologies produce huge amounts of short reads that consisting randomly fragmented DNA base pair strings. Assembling of those short reads poses a challenge on the mapping of reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a customized many-core hardware acceleration platform for short read mapping problems based on hash-index method. The processing core is highly customized to suite both 2-hit string matching and banded Smith-Waterman sequence alignment operations, while distributed memory interface with 3D–stacked architecture provides high bandwidth and low access latency for highly customized dataset partitioning and memory access scheduling. Conformal with original BFAST program, our design provides an amazingly 45,012 times speedup over software approach for single-end short reads and 21,102 times for paired-end short reads, while also beats similar single FPGA solution for 1466 times in case of single end reads. Optimized seed generation gives much better sensitivity while the performance boost is still impressive.     

Reconfigurable architectures for bio-sequence database scanning on FPGAs

Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to the rapid growth in the size of these databases. In this paper, we present a new approach to bio-sequence database scanning using re-configurable field-programmable gate array (FPGA)-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored toward the parameters of a query have been designed. We use customization opportunities available at run time to dynamically reconfigure the PEs to make better use of available resources. Our FPGA implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties compared to a standard desktop computing platform. We show how run-time reconfiguration can be used to further improve performance.     

哈特曼传感器仿真平台设计

为了实现波前处理机脱离以哈特曼传感器为核心的波前探测光学系统,独立地进行处理机算法的设计和验证,采用软、硬件结合的方式,设计了哈特曼传感器输出图像仿真平台。上位机仿真监控软件采用VC 和MATLAB 联合编程,根据哈特曼传感器工作原理和结构,仿真生成哈特曼图像,并完成与硬件电路交互命令和传输数据的功能。以FPGA 为核心的主控电路,完成发送响应信号、接收监控软件发送的读写指令、存储数据的功能,并根据实际CCD 时序实时输出标准Camera Link 接口格式的图像数据。经验证,软件仿真图像和实际输出相符;仿真平台输出表明硬件时序正确,满足设计速度要求。     

基于FPGA的高分辨率红外目标检测技术研究

本次研究面向红外对空预警探测领域的实际问题,开展高分辨率红外图像目标检测算法设计与工程化应用验证。文中研究设计了基于中值滤波、卷积滤波核形态学滤波等的目标检测算法,并基于FPGA平台进行硬件移植验证与测试。实验表明本文采用的方法可以实现对高分辨率红外图像的目标检测功能,并且基于FPGA硬件提升算法的运算速度,使算法在FPGA硬件平台上完成实时运算传输的要求。     

A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

This paper presents the design and implementation of the most parameterisable field-programmable gate array (FPGA)-based skeleton for pairwise biological sequence alignment reported in the literature. The skeleton is parameterised in terms of the sequence symbol type, i.e., DNA, RNA, or Protein sequences, the sequence lengths, the match score, i.e., the score attributed to a symbol match, mismatch or gap, and the matching task, i.e., the algorithm used to match sequences, which includes global alignment, local alignment, and overlapped matching. Instances of the skeleton implement the Smith–Waterman and the Needleman–Wunsch Algorithms. The skeleton has the advantage of being captured in the Handel-C language, which makes it FPGA platform-independent. Hence, the same code could be ported across a variety of FPGA families. It implements the sequence alignment algorithm in hand using a pipeline of basic processing elements, which are tailored to the algorithm parameters. This paper presents a number of optimizations built into the skeleton and applied at compile-time depending on the user-supplied parameters. These result in high performance FPGA implementations tailored to the algorithm in hand. For instance, actual hardware implementations of the Smith–Waterman algorithm for Protein sequence alignment achieve speedups of two orders of magnitude compared to equivalent standard desktop software implementations.      

一种高速LZW压缩算法FPGA硬件实现

在分析LZW算法的基础上,基于FPGA,设计了一个高速LZW压缩算法硬件加速电路,包含异步FIFO、状态机控制和双端口RAM三个主要部分。通过异步FIFO实现提高了数据传输速度；采用精简状态机模块提高了FPGA内部资源的利用率。在Kintex-7 XCKU060平台上验证了设计的正确性和加速特性。实验结果表明,数据压缩速率提升至366 Mbit/s,相比高性能通用处理器平台加速到9.1倍,能效比提升到65.5倍,可满足多种场景下实时无损压缩应用需求。     

Achieving Programming Model Abstractions for Reconfigurable Computing

This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models-and access to these computational models via high level languages-focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hardware removes the potential bottleneck of routing all system service requests through a central CPU.     

Hardware Acceleration of HMMER on FPGAs

We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for biological sequence alignment, based on profile hidden Markov models. We derive a flexible, generic, scalable hardware parallel architecture which can accelerate the core of hmmsearch by nearly two orders of magnitude, without modifying the original algorithm of this software. Our derivation is based on the expression of the algorithm as a set of recurrence equations, and we show in a systematic way how a very efficient parallel version of the algorithm can be found by combining scheduling, projection, partitioning, pipelining and precision analysis. We present the performance of the implementation of this parallel algorithm on a FPGA platform.     

基于ARM SoC的FPGA原型验证

ARM是目前SoC设计中应用最为广泛的高性价比的RISC处理器,FPGA原型验证是SoC有效的验证途径,FPGA原型验证平台能以实时的方式进行软硬件协同验证,从而可以缩短SoC的开发周期,提高验证工作的可靠性,降低SoC系统的开发成本.     

基于GPU加速的地震图像重建技术

针对目前地层层析成像算法中正演算法存在计算量大、计算速度慢的问题,以图像处理器(GPU)为核心,研究并实现了一种基于GPU平台的时域有限差分(FDTD)正演算法。CUDA是一种由NVIDIA推出的GPU通用并行计算架构,也是目前较为成熟的GPU并行运算架构。而FDTD正演算法本身在算法特性上满足并行的要求,二者的结合将极大地加速程序的计算速度。在基于标准Marmousi速度模型的正演模拟中,程序速度提升30倍,而GPU正演图像与CPU正演结果误差小于千分之一。算例表明CUDA可以大大加速目前的FDTD正演算法,并且随着GPU硬件自身的发展和计算架构的不断改进,加速效果还将进一步提升,这将有利于后续波形反演工作的进展。