基于时间交替采样技术的高速高精度ADC系统

介绍了一种基于时间交替采样结构的高速ADC系统,整个系统采用全数字方式实现时间交替采样技术,结构灵活多变。使用2片ADC芯片及外围电路、FPGA作为逻辑控制和数据接收缓存,来搭建时间交替ADC系统的硬件电路。其最高采样率可达400MSPS,采样精度为12位。通过分析时间交替ADC系统的原理及其通道误差特性,利用Matlab软件分析通道失配误差来源,对采集到的数据进行误差估计和校正     

多片ADC并行采集系统的误差时域测量与校正

并行时间交替采样是提高系统最大采样率的有效方法之一,但由于制造工艺的局限性,并行时间交替采样将不可避免地造成通道失配误差。本文利用正弦采样信号的时域特性,推导出一种快速而精确的算法,用于同时校正通道失配引起的增益误差、偏置误差和时间误差,并通过模拟仿真证明了算法的可行性。     

一种双通道时分交替ADC误差半盲校正算法

采样时间偏移误差校正一直是时分交替ADC各通道间失配校正的难点.传统的盲校正方式因采用自身信号作为参考信号,会在某些情况下出现校正出错的情形.在分数阶延时滤波器的基础上,通过在模拟信号中预留一定带宽给校正信号及其失真信息来实现采样时间误差的半盲校正,克服盲校正算法中出现校正出错的情形,并且采用变步长算法,实现了收敛速度和稳态误差的优化,最后给出相应的仿真结果.该算法为时分交替ADC的校正提供了一种新的思路.     

基于时域特性的并行系统的采样误差估计算法

为了降低并行时间交替采样系统中通道失配误差的 硬性,利用两个标准斜波 信号的时域特性,对斜波信号多次采样,采样点减去偏置误差得到的无偏置采样值,从而求 解采样点的时间误差和增益误差联立方程,计算时间和增益误差。本文算法的采样点数和推导计算量较少,是一种快速而 精确的工程实用算法;并使用Matlab对本文算法进行模拟仿真证明其可行性,并通过Farrow 结构的滤波器对估计所得的通道失配误差进行校正验证,校正后的无杂散动态范围(SFDR,spurious free dynamic range)至少达到50dB。     

分数倍延时数字滤波器设计

在时分交替ADC结构中,由于各子通道ADC采样时钟的偏差,导致通道采样信号误差,严重影响时分交替ADC的动态性能.针对时分交替ADC中子通道的时钟偏差,在信号精确重构的理论依据下,采用基函数分段拟合和频域逼近的方式设计延时低通滤波器.通过改变基函数的定义域,推导了[-Ts,0]内误差校正的理论基础,并结合基函数设计和频...     

基于代价函数的通道误差校正方法(英文)

方位多通道技术是合成孔径雷达(SAR)实现高分宽测的手段之一。在多通道系统中通道失配是不可避免的,这会导致SAR 图像模糊。已有的通道失配校正方法大多依赖于系统参数以及场景内容。参数的不确定性将会大大降低校正算法的稳定性。该文提出了一种改进的通道失配校正方法,根据失配产生的原因,将通道失配分为距离增益误差、脉冲采样时钟误差和传输相位误差3 项。前两项误差通过交替估计进行补偿,而传输相位误差则通过代价函数给予估计。该方法对成像场景的依赖较小,基于机载多通道验证平台实测数据的实验验证了该方法的有效性。      

一种并行AD采集系统的通道匹配误差研究

随着现代宽带雷达通讯的发展,对雷达回波信号的采集和目标的特征提取成为研究者关注的焦点.由于雷达回波的高频信号高达几十兆赫兹,时间交替采样模数转换器(ADC)系统便可在其中发挥重要作用,但这种结构会引入时间、增益和偏置3种主要的通道失配误差.该文对通道失配误差作了分析,建立了3种误差并存的非均匀采样信号频谱的数学模型,并在此基础上提出了该文的误差联合测量高效实时校正算法,最后在现场可编程门阵列(FPGA)中完成了整个算法的实现.     

高速OFDM系统中分时ADC失配误差校准技术

在高速OFDM接收机中利用分时ADC(TIADC)对接收信号进行采样,解决了单片ADC不能满足传输速率高达数Gb/s的通信系统需求的难题。由于TIADC各通道间的不匹配,时钟失配误差和增益失配误差大大影响了系统性能。在传输速率为4 Gb/s的OFDM系统中,利用4通道TIADC对接收信号进行采样,对两种失配误差和信道进行联合估计与均衡,并针对64QAM符号调制,对TIADC进行采样精度仿真。仿真结果证明,校准后的9位TIADC可以使系统误码率接近理想值。     

基于线下估计和线上补偿的时间交错采样ADC失配误差补偿方法

该文提出一种改进的时间交错采样模数转换器(TIADC)失配误差补偿方法。系统通过误差参数和简化的拉格朗日插值算法分别实现了对偏置、增益的失配误差补偿和采样时间的失配误差补偿。该补偿方法在FPGA中采用低复杂度的定点运算实现,在TIADC硬件平台中实现了对多通道ADC采样数据的线上校正。实验结果表明:所提改进方法在仿真环境下使无杂散动态范围提升了51 dB,并且在硬件实现过程中使SFDR优化达45 dB。在保持失配误差估计精度和补偿效果优良的前提下,该方法不仅降低了算法的计算复杂度,而且该补偿结构不受TIADC通道数目的限制。     

一种高速并行采样实时校正方法研究

并行交替采样带来的非均匀误差严重影响采集性能.本文建立了并行交替采集系统的数学模型,实现了一种幅度非均匀误差校正的归一化算法,在误差校正系统中引入可程控参考校正源,再利用查表法同时校正系统的偏置和增益失配误差,然后对时间非均匀性参数进行估计,并通过高精度可编程时钟延时网络对其修正.实验结果表明,该校正方法实时性好,降低了硬件设计难度和成本,提高了系统性能.     

Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system

To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system.     

Blind equalization of time errors in a time-interleaved ADC system

To significantly increase the sampling rate of an analog-to-digital converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the time mismatch errors. The estimation method requires no knowledge about the input signal, except that it should be band limited to the foldover frequency /spl pi//T/sub s/ for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the time errors. The Cramer-Rao bound (CRB) for the time error estimates is also calculated and compared to Monte Carlo simulations. The estimation method has also been validated on measurements from a real time-interleaved ADC system with 16 ADCs.     

Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs

In data acquisition systems, with help of time-interleaved analog-to-digital converter (TIADC) architecture, the maximum sample rate of the whole system can be increased efficiently. However, inevitable offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the sampling performance. In order to develop the mismatched TIADC structure, this paper first proposes a new time-domain algorithm to estimate the three aforementioned mismatch errors, and then puts forward a calibration method to calibrate the mismatch errors. Finally, numerical simulations are presented to verify the proposed estimation and calibration algorithm.     

基于混合滤波器组的时间交替采样技术

时间交替采样技术对通道失配误差十分敏感,而基于混合滤波器组的采样技术降低了对通道失配误差的敏感,但前端模拟分析滤波器的稳定性难于设计限制了其工程应用。结合时间交替和混合滤波器组采样技术,提出了一种易于工程实现的基于混合滤波器组的时间交替采样技术。仿真结果表明,该技术能显著提高采样系统的精度。     

Analysis and Implementation of a Time-Interleaved ADC Array for a Software-Defined UWB Receiver

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.     

多片ADC并行采集系统的增益误差补偿

时间交叉采样结构是提高模数转换系统采样率的一种有效途径。由于制造工艺的局限,这种结构会引入通道失配误差而限制系统的性能。通道失配误差包括偏置误差、增益误差和时间误差。提出了一种基于频域计算增益误差对其进行补偿的方法,并通过Matlab仿真验证了算法的有效性和可行性。