Analysis and design of a frequency-hopped spread-spectrumtransceiver for wireless personal communications

Personal communications services (PCS) require low-power radio technologies. One such transceiver architecture employing frequency-hopped spread-spectrum techniques is presented. System features such as antenna diversity with equal-gain combining and sequential hop combining are incorporated into the transceiver design to achieve robust wireless digital data transmission over fading channels. A direct-conversion architecture from radio frequency (RF) to baseband reduces the overall power consumption by eliminating intermediate frequency (IF) components. High-rate frequency hopping with frequency-shift keying (FSK) modulation is implemented using a direct digital frequency synthesis technique. A multiplierless correlation FSK detector, suitable for direct-conversion receivers, has been designed for quadrature noncoherent detection. Robust acquisition algorithms based on energy detection and pattern matching and tracking architectures using digital phase-locked loops are also described for system synchronization. The proposed transceiver is well-suited for low-power PCS applications and other portable wireless communications     

ADF4360—4原理及其在GPS信号源中的应用

通过分析频率合成器ADF4360—4的工作原理、性能特点及其典型应用,提出一种以FPGA芯片和频率合成器ADF4360—4为核心的GPS信号源系统,给出了总体及模块设计方案,并分模块进行了设计与实现。测试结果表明,以FPGA芯片为核心的基带／中频模块完成了GPS信号的BPSK调制和扩频调制,实现了GPS数字中频信号输出;以频率合成器ADF4360—4为核心的射频模块完成了上变频功能,实现了信号的射频调制。     

一种新颖的BPSK信号数字中频处理方法

介绍了一种适用于二相相移键控（ＢＰＳＫ）扩频调制信号的数字式处理方法。该方法通过对输入的ＢＰＳＫ信号在中频直接进行采样及数字相关,实现了全数字化处理。与传统采用的ＳＡＷ中频模拟处理方法和数字基带处理方法相比,该方法具有结构简单、工作温度范围宽和可靠性高等优点,可用于扩频通信、脉冲压缩雷达和敌我识别（ＩＦＦ）等系统。     

A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrumtransceiver IC [wireless LANs]

In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-μm N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5×3.5 mm². Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

多通道高速数字收发设计

雷达系统小型化的发展趋势要求收发分系统不断提高集成度以减小设备体积。文中介绍了一种多通道高速数字收发模块的设计方法,在一个模块上同时实现16通道射频波形产生和16通道中频采集功能。波形产生基于数字直接合成方式,工作频率1.6 GHz,可直接输出射频波形,波形控制参数可通过光纤接口调节。中频采样使用多通道模数转换器芯片实现,阻抗匹配电路保证了模数转换的性能。测试表明:模块性能指标满足系统使用需求,且已成功应用于某雷达系统中。     

基于多通道技术的数字收发单元设计

数字阵雷达具有通道数量多、设备量大的特点,其数字收发单元的小型化、可编程等优点,对降低系统复杂度、提高可靠性和降低成本起着关键的作用。随着数模混合集成电路的飞速发展,AD采样率和直接数字频率合成(DDS)输出频率均不断提高,数模信号的转换越来越靠近天线,意味着数字阵雷达将会实现真正意义上的全数字化。文中基于多通道模数转换、DDS和多通道同步技术,通过集成、高效的设计方案,完成数字收发单元的原理分析和电路集约化设计,对设计中的要点、难点及主要参数进行了简要阐述。     

A Microtransceiver for UHF Proximity Links Including Mars Surface-to-Orbit Applications

A low-volume low-mass low-power ultra-high-frequency radio transceiver for future planetary missions is described. The project targets a volume of less than 10 , mass of less than 50 grams, and power consumption of 50 mW on receive and 100 mW, 300 mW, or 3 W on transmit (for 10 mW, 100 mW, and 1 W output options). The transmitter design supports convolutionally coded binary phase-shift keying (BPSK), RC-BPSK, and quadrature phase-shift keying transmission from 1 to 256 kbps. Command/control instructions can be received at 2 or 8 kbps, with a sensitivity of better than 120 dBm. In addition to its low volume/mass/power features, temperature compensation to 100 C and radiation tolerance to 100 krad allow operation outside of thermally controlled, shielded enclosures, further reducing the mass and complexity of exploration vehicles. The design is described in a top-down format, beginning with system requirements and proceeding through digital modem algorithm development, discussion of the silicon-on-sapphire CMOS process used and elaboration of key blocks in the radio-frequency (RF) integrated circuit design. Techniques to address coupling between high-sensitivity RF and on-chip digital circuits are also presented, and test results are given for prototypes of all major functions. Although designed for the Martian environment, the transceiver is expected to be useful in other proximity links where a small low-power radio compatible with Prox-1 space-link protocols is desired.     

DAM中多通道数字收发的设计与实现

论述了多通道数字收发电路的设计方法与实现方案.详细介绍了以大容量FPGA为核心,基于高速DDS的多通道中频波形产生与基于多相滤波的多通道中频数字接收的工作原理.可实现最高采样频率为250 MS/s的八通道全数字同步接收,最高采样频率500 MS/s的八通道全数字波形同步产生,以及数据率为2.5 Gbit/s的高速数据实时传输.给出了数字接收与数字发射的测试结果,满足系统指标要求,电路实现简单、使用灵活,在数字阵列雷达中具有很好的通用性.     

一种C波段数字阵列模块设计与研究

介绍了一种C波段数字阵列模块的设计,该模块可应用于数字阵列雷达中,该模块包含独立可控的多个通道,易于实现收发数字波束形成,阵列模块中电路共用部分均采用集中供给,将混频器、滤波器等器件采用收发共用,使得阵列模块的集成度大幅提高。     

Development of design flow for multiported register files,which includes a cell library and a compiler for SOI 0.25-μm process

A typical design flow for a high-performance System-on-Chip usually includes memory compilers, which are implemented by different CAD producers for a given technology. These compilers allow to create automatically all file views for a memory unit using its configuration given by a user. However, there was no memory compiler for a 0.25-micron CMOS SOI process used in some our projects. At the same time, chips we were developing in this process had a wide variety of memories including register files. We developed new design approach and patented a multiported modular bitcell. Additionally, a schematic and layout library of basic cells was created to implement register files with different number of read and write ports. This gave rise to development of design flow and a program, which generates typical file views automatically.     

一种改进的BPSK载波同步方法的研究

对于在全数字接收机中一种软件实现的BPSK载波同步方法作了进一步的改进,克服了原有方法仅仅在理论上适合于存储空间和实时性的要求,而在实际工程上不能得到较好应用的弱点。提出了易于在DSP以及QPSK的直接序列扩展频谱系统中实现的方法,并在测试中达到了较好的性能。     

GPS射频信号源的设计与实现

在研究GPS信号结构的基础上,给出了GPS射频信号源的设计方案,并分模块进行了设计与实现.实验结果表明,基带/中频模块实现了GPS信号的BPSK调制和扩频调制,输出数字中频信号;射频模块实现了上变频功能,完成了信号的射频调制.     

一种宽频段扩频通信系统设计

以某数据链课题为背景,设计了一种基于STEL－2000A可编程扩频处理器的宽频段扩频基带和数字中频处理器方案。主要集中论述扩频模块的实现,硬件部分着重基带电路的接口设计,软件部分着重STEL－2000A初始化和通信接口编程。测试结果表明,该方案工作频段宽,设备简单,具有一定的实用性和可移植性。     

基于VHDL语言的并行数字相关器的数据通道设计

在采用并行数字相关器对直扩码进行解扩时,其数据通道设计十分关键。对数据通道使用流水线技术,可以提高其运算速度。整个数字相关器用VHDL语言来描述,经逻辑综合后,适配到FPGA芯片中。文中还给出布局布线后的时序仿真。     

一种基于Costas环的BPSK解调设计

设计了一种基于软件无线电思想的中频数字化接收机系统,该系统由数据采集模块、数字下变频（DDC）模块和数字解调模块构成。文中重点研究了基于Costas环的BPSK相干解调,并介绍了载波同步及BPSK解调的工作流程图,最后通过Simulink对BPSK解调原理进行了仿真验证。     

基于软件无线电的中频数字化直扩系统的设计与实现

本文根据直接序列扩频原理,给出了一种基于软件无线电思想的中频数字化直扩系统的设计方案,并采用可编程数字器件实现。实验结果表明该方法达到了设计要求,并具有良好的通用性和灵活性。     

一种小型高频无线收发系统的模块化设计

介绍了一种采用高集成度收/发芯片及编/解码芯片构成的高频无线收发系统的模块化设计方案.分析了设计高频无线收发模块的思路,采用最新的硬件编/解码电路实现了对载频信号的直接调制与解调,采用高标准、高品质的高频传输回路和编解码芯片,运用固定工作模式,使所有RF和IF均在电路中自动完成,大大简化了用于产生FM信号的控制逻辑,有效地提高了收发系统的集成度.     

基于FPGA的AIS中频收发信机设计及实现

针对海事自动识别系(Automatic Identification System,AIS)收发信机的信号处理主要采用专用芯片实现的现状,提出了一种中频数字化的替代方案,采用FPGA完成AIS中频收发信机的信号处理.重点研究了突发GMSK中频信号的调制、差分解调、位同步和帧同步的设计方法及实现过程.测试结果表明,采用并行化的数字信号处理,增强了设备的灵活性和可靠性,并提高了设备的性能.     

数字中频芯片的仿真研究

数字中频芯片通常间接地采取matlab的方式进行datapath滤波器等功能的设计和验证。在此基础上直接对数字中频RTL代码进行仿真验证研究,分别从单音、宽带、delay测试等方面进行阐述,结合快速傅立叶变换,综合运用python脚本工具分析结果。研究结果表明,相对于间接采用matlab仿真,直接的RTL代码仿真不仅能实现同样的测试功能,而且可以更好地提升代码覆盖率和功能覆盖率,进一步提升了验证质量。