Design of parallel concatenated convolutional codes

A parallel concatenated convolutional coding scheme consists of two constituent systematic: convolutional encoders linked by an interleaver. The information bits at the input of the first encoder are scrambled by the interleaver before entering the second encoder. The codewords of the parallel concatenated code consist of the information bits followed by the parity check bits of both encoders. Parallel concatenated codes (turbo codes), decoded through an iterative decoding algorithm of relatively low complexity, have been shown to yield remarkable coding gains close to theoretical limits. We characterize the separate contributions that the interleaver length and constituent codes give to the overall performance of the parallel concatenated code, and present some guidelines for the optimal design of the constituent convolutional codes     

Simultaneous zero-tailing of parallel concatenated codes

In a parallel concatenated convolutional code, an information sequence is encoded by a convolutional encoder, and an interleaved version of the information sequence is encoded by another convolutional encoder. We discuss the situation in which we require both convolutional encoders to end in the all-zero state. To do so, we have to split an information word in two parts. One part contains the true information bits, and the second part contains the so-called tail bits, which are special bits with values computed such that both encoders end in the all-zero state. Depending on the interleaver, a different number of tail bits are needed. By using a constructive method, we give a characterization of all interleavers for a prescribed number of tail bits. We explain the method of encoding. In addition, simulations have been carried out to investigate the performance of codes resulting from simultaneous zero-tailing. This shows that simultaneous zero-tailing is similar in performance as compared to previously known zero-tailing methods (but with fewer trellis termination bits) and that it is better than zero-tailing just one of the encoders.     

Multistage interconnection networks for parallel Viterbi decoders

We propose new multistage interconnection networks (MIN) for scalable parallel Viterbi decoder architectures. The architecture consists of the desired number of processing elements (PE) connected by the suggested MINs, thus allowing a tradeoff between complexity and speed. The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into the equivalent trellis with a perfect shuffle interconnection, and then applying a new decomposition of the perfect shuffle operator. This results in an efficient modular system and data flow is formed by the shuffling in a local PE memory and data exchange through a fixed interconnection between PEs. We suggest several solutions for 1/n and k/n rate codes, where k denotes the number of input bits shifting into k shift registers of the encoder and, at each cycle, the encoder produces n output bits as linear combinations of certain bits in the shift registers.     

Analysis, design, and iterative decoding of double seriallyconcatenated codes with interleavers

A double serially concatenated code with two interleavers consists of the cascade of an outer encoder, an interleaver permuting the outer codeword bits, a middle encoder, another interleaver permuting the middle codeword bits, and an inner encoder whose input words are the permuted middle codewords. The construction can be generalized to h cascaded encoders separated by h-1 interleavers, where h>3. We obtain upper bounds to the average maximum likelihood bit-error probability of double serially concatenated block and convolutional coding schemes. Then, we derive design guidelines for the outer, middle, and inner codes that maximize the interleaver gain and the asymptotic slope of the error probability curves. Finally, we propose a low-complexity iterative decoding algorithm. Comparisons with parallel concatenated convolutional codes, known as “turbo codes”, and with the proposed serially concatenated convolutional codes are also presented, showing that in some cases, the new schemes offer better performance     

Unveiling turbo codes: some results on parallel concatenated codingschemes

A parallel concatenated coding scheme consists of two simple constituent systematic encoders linked by an interleaver. The input bits to the first encoder are scrambled by the interleaver before entering the second encoder. The codeword of the parallel concatenated code consists of the input bits to the first encoder followed by the parity check bits of both encoders. This construction can be generalized to any number of constituent codes. Parallel concatenated schemes employing two convolutional codes as constituent codes, in connection with an iterative decoding algorithm of complexity comparable to that of the constituent codes, have been previously shown to yield remarkable coding gains close to theoretical limits. They have been named, and are known as, “turbo codes”. We propose a method to evaluate an upper bound to the bit error probability of a parallel concatenated coding scheme averaged over all interleavers of a given length. The analytical bounding technique is then used to shed some light on some crucial questions, which have been floating around in the communications community since the proposal of turbo codes     

Design and decoding of optimal high-rate convolutional codes

This correspondence deals with the design and decoding of high-rate convolutional codes. After proving that every (n,n-1) convolutional code can be reduced to a structure that concatenates a block encoder associated to the parallel edges with a convolutional encoder defining the trellis section, the results of an exhaustive search for the optimal (n,n-1) convolutional codes is presented through various tables of best high-rate codes. The search is also extended to find the "best" recursive systematic convolutional encoders to be used as component encoders of parallel concatenated "turbo" codes. A decoding algorithm working on the dual code is introduced (in both multiplicative and additive form), by showing that changing in a proper way the representation of the soft information passed between constituent decoders in the iterative decoding process, the soft-input soft-output (SISO) modules of the decoder based on the dual code become equal to those used for the original code. A new technique to terminate the code trellis that significantly reduces the rate loss induced by the addition of terminating bits is described. Finally, an inverse puncturing technique applied to the highest rate "mother" code to yield a sequence of almost optimal codes with decreasing rates is proposed. Simulation results applied to the case of parallel concatenated codes show the significant advantages of the newly found codes in terms of performance and decoding complexity.     

Rate k/(k+1) punctured convolutional encoders

G.D. Forney (1970, 1975) defined a minimal encoder as a polynomial matrix G such that G generates the code and G has the least constraint length among all generators for the code. Any convolutional code can be generated by a minimal encoder. High-rate k(k+1) punctured convolutional codes were introduced to simplify Viterbi decoding. An ordinary convolutional encoder G can be obtained from any punctured encoder. A punctured encoder is minimal if the corresponding ordinary encoder G is minimal and the punctured and ordinary encoders have the same constraint length. It is shown that any rate k/(k+1), noncatastrophic, antipodal punctured encoder is a minimal encoder.<>     

Serial concatenation of interleaved codes: performance analysis,design, and iterative decoding

A serially concatenated code with interleaver consists of the cascade of an outer encoder, an interleaver permuting the outer codewords bits, and an inner encoder whose input words are the permuted outer codewords. The construction can be generalized to h cascaded encoders separated by h-1 interleavers. We obtain upper bounds to the average maximum-likelihood bit error probability of serially concatenated block and convolutional coding schemes. Then, we derive design guidelines for the outer and inner encoders that maximize the interleaver gain and the asymptotic slope of the error probability curves. Finally, we propose a new, low-complexity iterative decoding algorithm. Throughout the paper, extensive comparisons with parallel concatenated convolutional codes known as “turbo codes” are performed, showing that the new scheme can offer superior performance     

High-performance VLSI architecture for the Viterbi algorithm

The Viterbi (1967) algorithm (VA) is known to be an efficient method for the realization of maximum-likelihood (ML) decoding of convolutional codes. The VA is characterized by a graph, called a trellis, which defines the transitions between states. To define an area efficient architecture for the VA is equivalent to obtaining an efficient mapping of the trellis. We present a methodology that permits the efficient hardware mapping of the VA onto a processor network of arbitrary size. This formal model is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated, optimizing the use of the PEs and the communications. Therefore, the algorithm is mapped onto a column of processing elements and an optimal design solution is obtained for a particular set of area and/or speed constraints. Furthermore, the management of the surviving path memory for its mapping and distribution among the processors was studied. As a result, we obtain a regular and modular design appropriate for its VLSI implementation in which the only necessary communications between processors are the data recirculations between stages     

基于级联码的信道编译码设计与FPGA实现

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点.分别采用并行和串行结构实现.其中RS译码采用欧几里德算法,卷积译码采用维特比算法.同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

Convolutional codes I: Algebraic structure

A convolutional encoder is defined as any constant linear sequential circuit. The associated code is the set of all output sequences resulting from any set of input sequences beginning at any time. Encoders are called equivalent if they generate the same code. The invariant factor theorem is used to determine when a convolutional encoder has a feedback-free inverse, and the minimum delay of any inverse. All encoders are shown to be equivalent to minimal encoders, which are feedback-free encoders with feedback-free delay-free inverses, and which can be realized in the conventional manner with as few memory elements as any equivalent encoder, Minimal encoders are shown to be immune to catastrophic error propagation and, in fact, to lead in a certain sense to the shortest decoded error sequences possible per error event. In two appendices, we introduce dual codes and syndromes, and show that a minimal encoder for a dual code has exactly the complexity of the original encoder; we show that systematic encoders with feedback form a canonical class, and compare this class to the minimal class.     

Punctured recursive convolutional encoders and their applicationsin turbo codes

Puncturing is the predominant strategy to construct high code rate convolutional encoders, and infinite impulse response (IIR) convolutional encoders are an essential building block in turbo codes. In this paper, various properties of convolutional encoders with these characteristics are developed. In particular the closed-form representation of a punctured convolutional encoder and its generator matrix is constructed, necessary and sufficient conditions are given such that the punctured encoders retain the IIR property, and various lower bounds on distance properties, such as effective free distance, are developed. Finally, necessary and sufficient conditions are given on the inverse puncturing problem: representing a known convolutional encoder as a punctured encoder     

卷积码Viterbi译码算法的FPGA实现

探讨了卷积码Viterbi译码的FPGA实现问题。在Viterbi译码算法中，提出了减少路径量度的位数和流水线回索法的幸存路径等方法，能有效地减少存储量、降低功耗、提高速度，使得K=7的Viterbi译码算法可在以单片FPGA为主的器件上实现。     

LTE系统中截尾卷积码译码算法研究及仿真性能分析

在LTE的下行控制信道和广播信道中采用了截尾卷积编码方式,本文介绍了LTE系统中采用的卷积编码器以及广播信道架构,详细分析了截尾卷积码的两种常用译码算法,文章提出了一种改进循环译码算法,在基于LTE-PBCH信道链路中对各种译码算法进行仿真,仿真测试结果表明,截尾卷积码可满足LTE信道对高速率业务的要求,双回溯循环译码算法的译码性能最佳。     

Design of parallel fault-secure encoders for systematic cyclic block transmission codes

In this paper, we consider the problem of designing parallel fault-secure encoders for various systematic cyclic linear codes used in data transmission. It is assumed that the data to be encoded before transmission are stored in a fault-tolerant RAM memory system protected against errors using a cyclic linear error detecting and/or correcting code. The main idea relies on taking advantage of the RAM check bits to control the correct operation of the cyclic code encoder as well. A slightly modified encoder allows not only for encoding the transmission data stream but also, independently and in parallel, to generate the reference check bits which allow for concurrent error detection in the encoder itself. The error detection capacity proves to be effective and grants good levels of protection as shown by error injection campaigns on encoders for various standard linear cyclic error detecting and error correcting codes. Moreover, the complexity evaluation of the FPGA implementations of the encoders shows that their fault-secure versions compare favorably against the unprotected ones, both with respect to hardware complexity and the maximal frequency of operation.     

Simplified trellis decoder

A new simplified trellis decoder (STD) Viterbi-type algorithm is proposed for fast trellis decoding of rate K/K+1 binary convolutional codes. Viterbi algorithm (VA) computation is dominated by add-compare-select (ACS) operations when k⩾2. The STD can substantially reduce the number of ACS operations and allow for a trade-off between the computational load and the performance of the decoder, The STD is analyzed and simulated for a four-dimensional (4-D) rate 4/5 64-state convolutional encoder specified by the ITU-T V.34 modem recommendation     

The performance of rate-compatible punctured convolutional codesfor digital mobile radio

The unequal error protection capabilities of convolutional codes belonging to the family of rate-compatible punctured convolutional codes (RCPC codes) are studied. The performance of these codes is analyzed and simulated for the first fading Rice and Rayleigh channels with differentially coherent four-phase modulation (4-DPSK). To mitigate the effect of fading, interleavers are designed for these unequal error protection codes, with the interleaving performed over one or two blocks of 256 channel bits. These codes are decoded by means of the Viterbi algorithm using both soft symbol decisions and channel state information. For reference, the performance of these codes on a Gaussian channel with coherent binary phase-shift keying (2-CPSK) is presented. A number of examples are provided to show that it is possible to accommodate widely different error protection levels within short information blocks. Unequal error protection codes for a subband speech coder are studied in detail. A detailed study of the effect of the code and channel parameters such as the encoder memory, the code rate, interleaver depth, fading bandwidth, and the contrasting performance of hard and soft decisions on the received symbols is provided     

Improving the distance properties of turbo codes using a third component code: 3D turbo codes - [transactions letters]

Thanks to the probabilistic message passing performed between its component decoders, a turbo decoder is able to provide strong error correction close to the theoretical limit. However, the minimum Hamming distance (d_min) of a turbo code may not be sufficiently large to ensure large asymptotic gains at very low error rates (the so-called flattening effect). Increasing the d_min of a turbo code may involve using component encoders with a large number of states, devising more sophisticated internal permutations, or increasing the number of component encoders. This paper addresses the latter option and proposes a modified turbo code in which a fraction of the parity bits are encoded by a rate-1, third encoder. The result is a noticeably increased d_min, which improves turbo decoder performance at low error rates. Performance comparisons with turbo codes and serially concatenated convolutional codes are given.     

Systolic array processing of the Viterbi algorithm

Results on efficient forms of decoding convolutional codes based on the Viterbi algorithm by using systolic arrays are presented. Various properties of convolutional codes are discussed. A technique called strongly connected trellis decoding is introduced to increase the efficient utilization of all the systolic array processors. Issues dealing with the composite branch metric generation, survivor updating, overall system architecture, throughput rate, and computational overhead ratio are also investigated. The scheme is applicable to both hard and soft decoding of any rate b/n convolutional code. It is shown that as the length of the code becomes large, the systolic Viterbi decoder maintains a regular and general interconnection structure as well as moderate throughput rate gain over the sequential Viterbi decoder     

VLSI Structures for Viterbi Receivers: Part I--General Theory and Applications

A taxonomy of VLSI grid model layouts is presented for the implementation of certain types of digital communication receivers based on the Viterbi algorithm. We deal principally with networks of many simple processors connected to perform the Viterbi algorithm in a highly parallel way. Two interconnection patterns of interest are the "shuffleexchange" and the "cube-connected cycles." The results are generally applicable to the development of area-efficient VLSI circuits for decoding: convolutional codes, coded modulation with multilevel/phase signals, punctured convolutional codes, correlatively encoded MSK signals and for maximum likelihood sequence estimation ofM-ary signals on intersymbol interference channels. In a companion paper, we elaborate on how the concepts presented here can be applied to the problem of building encoded MSK Viterbi receivers. Lower bounds are established on the product (chip area) * (baud rate)^-2and on the energy consumption that any VLSI implementation of the Viterbi algorithm must obey, regardless of the architecture employed or the intended application.