晶圆切割崩裂的成因和预防措施探讨

随着电子技术的发展,对集成电路封装工艺的要求越来越高。封装核心工序中划片工序造成的晶圆崩裂问题是一个工艺难点,也是制约封装行业发展的瓶颈之一。本文主要对晶圆崩裂的机理进行了分析,探讨了晶圆切割过程中影响其崩裂的各关键因素,从而针对性的提出了预防晶圆崩裂的有效方法。     

超薄圆片划片工艺探讨

集成电路小型化正在推动圆片向更薄的方向发展,超薄圆片的划片技术作为集成电路封装小型化的关键基础工艺技术,显得越来越重要,它直接影响产品质量和寿命。本文从超薄片划片时常见的崩裂问题出发,分析了崩裂原因,简单介绍了目前超薄圆片切割普遍采用的STEP切割工艺。另外,针对崩裂原因,还从组成划片刀的3个要素入手分析了减少崩裂的选刀方法。     

超高亮度发光二极管芯片切割技术

介绍了超高亮度发光二极管(UHB-LED)芯片切割工艺中砂轮切割、金刚刀划片及激光切割的应用情况、工艺原理、工艺特点和发展前景.结合生产实践,对比和分析了不同切割工艺的优缺点,针对不同切割生产工艺中存在的芯片正崩、芯片背崩、芯片脱落以及划片裂片不良等问题进行了探讨并提出了解决方法.指出激光切割技术是LED芯片切割工艺发展的必然趋势.     

微水刀激光划片机的切割原理

随着划片机市场的不断扩大和半导体行业的飞速发展,划片机的切割质量直接影响着产品的产量、成品率和效率,微水刀激光划片机逐渐占领半导体切割工艺的主要市场。本文将对微水刀激光划片机的切割原理和技术特点做初步探讨。     

CO2激光在陶瓷划片,切割及打孔上的应用研究

研制了一台ＣＯ２激光陶瓷划片，切割，打孔机，确定了不同厚度陶瓷片的划片、切割、打孔工艺。     

硅的深度反应离子刻蚀切割可行性研究

评估了使用深反应离子刻蚀工艺来进行晶圆的切割,用于替代传统的刀片机械切割方式。结果表明,使用深反应离子刻蚀工艺,晶圆划片道内的硅通过等离子化学反应生成气态副产物被去除,从而避免了芯片侧面的机械损伤。切割后整个晶圆没有出现颗粒沾污,芯片边缘没有崩角以及开裂等损伤。该工艺还可以适用于更窄的划片道切割要求。     

LTCC基板砂轮划片工艺研究

通过正交试验确认了导致LTCC(低温共烧陶瓷)基板砂轮划片背面崩边的主要因素,基于对各个主要因素的分析,优化了砂轮划片方案,有效地解决了背面崩边问题,获得了高质量的划片效果。     

ADT7100划片机的使用和维护

划片是电子器件封装工艺中重要的工艺之一,是将一整片晶圆切割成每个独立的个体,芯片切割的质量直接影响封装的质量和器件的性能。划片机有SAW类型的划片机,还有激光划片机。作者多年以来一直从事划片工艺,现对在用的ADT7100机器的结构、维修和维护作介绍,同时简单分析划片工艺。     

"魔法"激光划片-MAHOH

划片工艺概述划片工艺隶属于晶圆加工的封装部分,它不仅仅是芯片封装的核心关键工序之一,而且是从圆片级的加工(即加工工艺针对整片晶圆,晶圆整片被同时加工)过渡为芯片级加工(即加工工艺针对单个芯片)的地标性工序。从功能上来看,划片工艺通过切割圆片上预留的切割划道(street),将众多的芯片相互分离开,为后续正式的芯片封装做好最后一道准备。划片工艺的发展历程在最早期,人们通过划片机(Scriber)来进行芯片的切割分离,其过程类似于今天的手工划玻璃,用金刚刀在被切割晶圆的表面刻上一道划痕,然后再通过裂片工艺使晶圆沿划痕分割成单个芯…     

硅片划片加工

<正> 硅片制备后经过一系列半导体工艺,制成规则排列的器件。最后采用划片工艺,将器件切割分离,供线焊封装。划片方法有划裂、激光划片、金刚石划片。古老的划裂法无法得到整齐切缝,致使高速粘片机无法准确取放,并常常伴有裂纹倾向。划裂后还要作第二步裂片,生产率低。激光划片速度很快,但是设备投资、维修费用很高,划片中     

IC封装中引起芯片裂纹的主要因素

芯片裂纹是半导体集成电路封装过程中最严重的缺陷之一。由于芯片裂纹最初发生在芯片的背面,而且有时要在高倍显微镜下才能观察到,所以这种缺陷在很多情况下不易被发现。文章主要介绍和探讨了IC封装过程中引起芯片裂纹的主要原因。划片刀速度、装片顶针位置／顶针高度和吸嘴压力、塑封框架不到位以及切筋打弯异常等都会引起芯片裂纹,从而在从IC焊接到PCB板或使用过程中出现严重的失效和可靠性质量问题。只有了解了导致芯片裂纹的各种因素,半导体集成电路封装厂商才能采取针对性的预防措施杜绝芯片裂纹这种致命的缺陷。     

金刚刀划片过程中的崩缺问题应对方案

本文针对金刚刀划片崩缺问题,对比双刀划片和单刀划片试验,分析了崩缺产生的原因,提出了窄划片槽晶圆金刚刀划片崩缺问题的应对方案。金刚刀划片采用双刀划片降低崩缺风险优于单刀划片工艺,双刀划片刀宽度越窄有利于降低崩缺,第一刀切深1/3厚度有利于降低崩缺风险。     

Study on the effects of wafer thinning and dicing on chip strength

Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45/spl deg/ wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-/spl mu/m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.     

Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping

Thin wafers of 100-/spl mu/m thickness laminated with die-attach film (DAF) was diced using a standard sawing process and revealed a low chipping crack resistance. Wafers laminated with conductive DAF shows greater chipping compared to nonconductive DAF and bare silicon wafer. It was found through scanning electron microscopy (SEM) micrographs, energy dispersive X-ray (EDX) analysis, and atomic force microscopy (AFM) that silver fillers in the conductive DAF was the cause of excessive blade loading which resulted in bad chipping quality. To reduce chipping/cracking induced by sawing, an alternative double-pass sawing method was developed and is explained in the paper. The methodology of this study discusses a double-pass method, where the first pass dice through the wafer and varied the percentage of DAF thickness cut. Best results were achieved when dicing through the wafer and 0% of DAF, followed by a full separation in the second pass. Approximately 80% of chipping reduction compared to conventional single pass.     

A hybrid wafer-dicing process for GaAs MMIC production

A dicing process for GaAs MMIC (monolithic microwave integrated circuit) wafers using spin-on wax for wafer mounting and a hybrid process of wet chemical etching/mechanical sawing for chip dicing is described. This process minimizes ragged chip edges and reduces generation of microcracks in addition to the elimination of the plated gold burrs on the backside of the diced MMIC chips. This process gives a uniformity of -3 μm across a 2-in wafer following the completion of the whole backside process. This GaAs chip dicing technique is amenable to production because it exhibits both a very high chip yield (>90%) and nearly flawless edges     

Temperature measurement of metal-coated silicon wafers bydouble-pass infrared transmission

We report the measurement of the temperature of metal-coated silicon wafers by a double-pass infrared transmission technique. Infrared light incident on the backside of the wafer passes through the wafer, and is re-emitted out the backside after reflecting off the metal surface on the front side of the wafer. The temperature is inferred by the change in the re-emitted signal due to absorption in the wafer. The work has been demonstrated on double-polished wafers from 100°C to 550°C using wavelengths from 1.1 to 1.55 μm. A method for overcoming limitations of the present arrangement for wafers with a rough backside is proposed     

多线切割工艺中晶片翘曲度的控制

翘曲度是鉴别晶片几何参数好坏的重要指标之一.采用逐点扫描法对多线切割制备的晶片翘曲度分布进行了测量.通过对切割线张力、砂浆使用次数、切割速度等影响翘曲度的主要因素进行实验分析,阐述了产生的原因,并得出了翘曲度的分布规律.针对影响翘曲度的主要因素,根据其分布规律调整相应的切割工艺条件,可较好地控制晶片的翘曲度.虽是针对Si单晶加工中出现的实验情况进行分析,但该结论完全可用于Ge、GaAs等其他晶体的加工中.     

一种实用的磷化铟MMIC背面工艺技术

采用湿法技术发展了磷化铟MMIC的背面通孔刻蚀工艺,PMMA用作粘片剂,InP衬底粘附于玻璃版上,溅射钽膜用作湿法刻蚀掩膜,HCl+H3PO4腐蚀液实现100μm的通孔腐蚀.已证实这种湿法通孔工艺宽容度大,精确可控.     

超薄硅片贴膜抛光技术研究

伴随着集成电路芯片的不断轻薄化,各种高质量的超薄抛光片衬底需求日益增加.介绍了一种简捷、方便的手动贴膜方法,并将其应用在200μm厚7.6 cm硅单晶免清洗单面抛光片加工过程中,通过与粘蜡抛光相比较,发现贴膜抛光实用性更强、成品率更高且成本更低.     

SiC晶圆背面激光退火工艺研究

降低芯片背面金属-半导体欧姆接触电阻是有效提高器件性能的方式之一。采用650 V SiC肖特基势垒二极管(SBD)工艺,使用波长355 nm不同能量的脉冲激光进行退火实验,利用X射线衍射(XRD)和探针台对晶圆背面镍硅合金进行测量分析,得出最佳能量为3.6 J/cm²。退火后采用扫描电子显微镜(SEM)观察晶圆背面碳团簇,针对背面的碳团簇问题,在Ar;气氛下对晶圆进行了表面处理,使用SEM和探针台分别对两组样品的表面形貌和电压-电流特性进行了对比分析。实验结果表明,通过表面处理可以有效降低表面的碳含量,并且使器件正向压降均值降低了6%,利用圆形传输线模型(CTLM)测得芯片的比导通电阻为9.7×10^-6Ω·cm²。器件性能和均匀性都得到提高。