关态应力下 P- MOSFETs的退化

研究了沟长从 0 .5 2 5 μm到 1.0 2 5 μm9nm厚的 P- MOSFETs在关态应力 ( Vgs=0 ,Vds<0 )下的热载流子效应 .讨论了开态和关态应力 .结果发现由于在漏端附近存在电荷注入 ,关态漏电流在较高的应力后会减小 .但是低场应力后关态漏电流会增加 ,这是由于新生界面态的作用 .结果还发现开态饱和电流和阈值电压在关态应力后变化很明显 ,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响 .Idsat的退化可以用函数栅电流 ( Ig)乘以注入的栅氧化层电荷数 ( Qinj)的幂函数表达 .最后给出了基于 Idsat退化的寿命预测模型     

低压5V pMOS器件在不同栅偏置应力下的热载流子注入退化机理研究

研究了低压pMOS器件热载流子注入HCI（hot-carrier injection）退化机理,分析了不同的栅压应力下漏极饱和电流（Idsat）退化出现不同退化趋势的原因。结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压（Vth）,导致Idsat的上升。当栅压为-7.5V时,界面态的产生是导致退化的主要因素,在栅压为-2.4V的应力条件下,电子注入在热载流子退化中占主导作用。     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现，短沟薄栅氧LDD nMOSFET（Lg=0.18μm，Tox=3.2nm）在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子（DAHC）应力下的器件寿命要短，这与通常认为的DAHC应力（最大衬底电流应力）下器件退化最严重的理论不一致．因此，这种热载流子应力导致的器件退化机理不能用幸运电子模型（LEM）的框架理论来解释．认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子，在Si-SiO2界面产生界面陷阱(界面态)的区域，由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的．     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2 .1nm ,栅长为0 .135μm的p MOSFET中HAL O掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HAL O掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HAL O掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究.研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化.应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加,击穿电荷减少,也会造成关态漏泄漏电流的退化.栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生.热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动,这解释了源区一侧栅氧化层损伤的产生原因.     

不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2.1nm,栅长为0.135μm的pMOSFET中HALO掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HALO掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HALO掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

Sence-Switch型pFLASH单元制备及特性

基于0.13 μm eFLASH工艺技术,成功制备了Sence-Switch型pFLASH单元,并对其性能进行了研究.该单元由两个共享浮栅和控制栅的编程/擦除管(T1)和信号传输管(T2)组成,采用带带遂穿(BTBT)编程方式和福勒-诺德海姆(FN)遂穿擦除方式实现了其“开/关”态功能,并对其“开/关”态特性进行表征,同时,研究了其耐久性和电荷保持特性.实验结果表明,该单元具有较优的“开/关”态特性和电参数一致性,T1/T2管阈值窗口的均值、均一性分别约为9.2V和2.4％;在工作电压为-1.5V条件下,T2管“关”态的漏电流均在1 pA/μm以下,T2管“开”态的驱动电流均值为116.22 μA/μm,均一性为5.61％;该单元循环擦/写次数可达10 000次.同时,在25℃的“开/关”态应力条件下,该Sence-Switch型pFLASH单元寿命大于10年.     

SOI NMOSFET沟道热载流子的应力损伤

研究了沟道热载流子应力所引起的SOI NMOSFET的损伤．发现在中栅压应力（Vg≈Vd／2）和高栅压应力（Vg≈Vd）条件下,器件损伤表现出单一的幂律规律;而在低栅压应力（Vgs≈Vth）下,多特性的退化规律便会表现出来．同时,应力漏电压的升高、应力时间的延续都会导致退化特性的改变．这使预测SOI器件的寿命变得非常困难．     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

Mechanism of device degradation in n- and p-channel polysiliconTFTs by electrical stressing

The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation     

AlGaN/GaN High Electron Mobility Transistor degradation under on- and off-state stress

AlGaN/GaN High Electron Mobility Transistors (HEMTs) with various gate lengths have been step-stressed under both on- and off-state conditions. On-state, high power stress tests were performed on 0.17 μm gate length HEMTs and a single 5 μm spaced TLM pattern. Significant degradation of the submicron HEMTs as compared to the excellent stability of the TLM patterns under the same stress conditions reveal that the Schottky contact is the source of degradation. Off-state stress showed a linear relationship between the critical degradation voltage and gate length, though two dimensional ATLAS/Blaze simulations show that the maximum electric field is similar for all gate lengths. Additionally, as the drain bias was increased, the critical voltage decreased. However, the cumulative bias between the gate and drain remained constant, further indicating that the electric field is the main mechanism for degradation.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET

The effects of gamma irradiation on the shallow trench isolation(STI)leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device’s gate length.The three-transistor model(one main transistor with two parasitic transistors)can provide us with a brief understanding of the dependence on gate length.     

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

Off-state breakdown effects on gate leakage current in powerpseudomorphic AlGaAs/InGaAs HEMTs

The effects of off-state breakdown on characteristics of power AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) are investigated in detail. While the gate leakage current is substantially decreased after breakdown stress, no obvious changes in drain-to-source current and transconductance are observed. Prior to breakdown stress, gate leakage current shows a nearly ideal 1/f noise characteristic with an Ig² dependence, suggesting a surface generation-recombination current from the interface of the passivation layer. After stress, the gate current noise can be drastically reduced. The results suggest an alternative for alleviating the gate leakage current in PHEMTs