抑制 SOIp- MOSFET中短沟道效应的 GeSi源 /漏结构

提出在 SOI p- MOSFET中采用 Ge Si源 /漏结构 ,以抑制短沟道效应 .研究了在源、漏或源与漏同时采用 Ge Si材料对阈值电压漂移、漏致势垒降低 (DIBL)效应的影响 ,并讨论了 Ge含量及硅膜厚度变化对短沟道效应及相关器件性能的影响 .研究表明 Ge含量应在提高器件驱动电流及改善短沟道效应之间进行折中选择 .对得到的结果文中给出了相应的物理解释 .随着器件尺寸的不断缩小 ,Ge Si源 /漏结构不失为 p沟 MOS器件的一种良好选择     

SiGe source/drain structure for the suppression of theshort-channel effect of sub-0.1-μm p-channel MOSFETs

A bandgap engineering technique is proposed for the suppression of the short-channel effect (SCE) and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation. The drain-induced barrier lowering (DIBL) and the charge sharing are suppressed by the presence of the valence band discontinuity between the SiGe source/drain and Si channel. In order to obtain the full advantage of this structure, it is necessary to locate the SiGe layers both at the source/drain regions and the SiSe/Si interface at the pn junction or inside the channel region. The effectiveness increases with the increase of the valence band discontinuity (Ge concentration). As a result of the suppression of the SCE and the reduction of the minimum gate length, the drain current increases, and thus high-speed operation can be realized with this technique     

SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。     

异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*

本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型．并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究．该模型中考虑以下参数：金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分．结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL．同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率．此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高．数值模拟器ISE验证了该模型的正确性．     

应变硅MOSFET沟道应变的有限元研究

本文报道了利用有限元计算和动力学大角度会聚束电子衍射模拟的方法研究了应变硅场效应晶体管沟道中的应变分布.沟道压应变是利用预非晶化源漏区锗离子注入应变诱导工艺技术引入的.有限元计算结果显示,器件的源漏区很低的锗注入剂量在沟道区的顶层造成了很大的压应变,而且在沟道和硅衬底中间形成一个应变过渡层.大角度会聚束电子衍射的动力学模拟结果与有限元计算结果符合很好.     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

Doping and processing epitaxial GexSi1−x films on Si(100) by ion implantation for Si-based heterojunction devices applications

The question of whether one can effectively dope or process epitaxial Si(100)/GeSi heterostructures by ion implantation for the fabrication of Si-based heterojunction devices is experimentally investigated. Results that cover several differention species (B, C, Si, P, Ge, As, BF₂, and Sb), doses (10¹³ to 10¹⁶/cm²), implantation temperatures (room temperature to 150°C), as well as annealing techniques (steady-state and rapid thermal annealing) are included in this minireview, and the data are compared with those available in the literature whenever possible. Implantation-induced damage and strain and their annealing behavior for both strained and relaxed GeSi are measured and contrasted with those in Si and Ge. The damage and strain generated in pseudomorphic GeSi by room-temperature implantation are considerably higher than the values interpolated from those of Si and Ge. Implantation at slightly elevated substrate temperatures (e.g., 100°C) can very effectively suppress the implantation-induced damage and strain in GeSi. The fractions of electrically active dopants in both Si and GeSi are measured and compared for several doses and under various annealing conditions. Solid-phase epitaxial regrowth of GeSi amorphized by implantation has also been studied and compared with regrowth in Si and Ge. For the case of metastable epi-GeSi amorphized by implantation, the pseudomorphic strain in the regrown GeSi is always lost and the layer contains a high density of defects, which is very different from the clean regrowth of Si(100). Solid-phase epitaxy, however, facilitates the activation of dopants in both GeSi and Si, irrespective of the annealing techniques used. For metastable GeSi films that are not amorphized by implantation, rapid thermal annealing is shown to outperform steady-state annealing for the preservation of pseudomorphic strain and the activation of dopants. In general, defects generated by ion implantation can enhance the strain relaxation process of strained GeSi during post-implantation annealing. The processing window that is optimized for ion-implanted Si, therefore, has to be modified considerably for ion-implanted GeSi. However, with these modifications, the mature ion implantation technology can be used to effectively dope and process Si/GeSi heterostructures for device applications. Possible impacts of implantation-induced damage on the reliability of Si/GeSi heterojunction devices are briefly discussed.     

Potentialities and basic principles of controlling the plastic relaxation of GeSi/Si and Ge/Si films with stepwise variation in the composition

GeSi/Si heterostructures consisting of a plastically relaxed layer that includes various fractions of Ge and which is grown on Si (001) span the values of the lattice parameter from equal to that in silicon to equal to that in germanium. The corresponding substrates are conventionally referred to as artificial. A number of methods exist for growing high-quality GeSi layers with as large as 100% of Ge on Si (001) substrates through an intermediate GeSi layer with a varying composition. However, it is desirable in a number of cases to have ultrathin (<1 μm) GeSi and Ge layers directly on the Si (001) substrate for practical applications. The results of new methods such as the use of a buffer Si layer grown at a comparatively low temperature (300–400°C) in plastic relaxation of the GeSi/Si(001) heterostructures and also the use of surfactants (antimony and hydrogen) are analyzed. The examples of artificial introduction of centers for origination of misfit dislocations as an alternative to their introduction from the rough surface are considered. It can be concluded that, in order to expand the range of potentialities of growing perfect plastically relaxed GeSi (001) films, it is necessary to (i) make it possible to form in a controlled manner the centers for origination of the misfit dislocations and (ii) retard or completely suppress the transition of the growth mechanism from two-to three-dimensional in order to prevent the formation of additional misfit dislocations from the surface of the stressed film and, correspondingly, additional threading dislocations.     

Suppression of the floating-body effect in partially-depleted SOIMOSFETs with SiGe source structure and its mechanism

SiGe layers were formed in source regions of partially-depleted 0.25-μm SOI MOSFETs by Ge implantation, and the floating-body effect was investigated for this SiGe source structure. It is found that the increase of the Ge implantation dosage suppresses kinks in I_d-V_d characteristics and that the kinks disappear for devices with a Ge dose of 3×10¹⁶ cm^-2. The lowering of the drain breakdown voltage and the anomalous decrease of the subthreshold swing are also suppressed with this structure. It is confirmed that this suppression effect originates from the decrease of the current gain for source/channel/drain lateral bipolar transistors (LBJTs) with the SiGe source structure. The temperature dependence of the base current indicates that the decrease of the current gain is ascribed to the bandgap narrowing of the source region     

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation.     

SOI CMOS器件研究

利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。     

Co/a-GeSi/Ti/Si多层薄膜固相反应外延生长CoSi_2薄膜

研究了在 Co/Ti/Si结构中加入非晶 Ge Si层对 Co Si2 /Si异质固相外延的影响 ,用离子束溅射方法在Si衬底上制备 Co/Ge Si/Ti/Si结构多层薄膜 ,通过快速热退火使多层薄膜发生固相反应。采用四探针电阻仪、AES、XRD、RBS等方法进行测试。实验表明 ,利用 Co/Ge Si/Ti/Si固相反应形成的 Co Si2 薄膜具有良好的外延特性和电学特性 ,Ti中间层和非晶 Ge Si中间层具有促进和改善 Co Si2 外延质量 ,减少衬底耗硅量的作用。Ge原子的存在能够改善外延 Co Si2 薄膜的晶格失配率     

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40?nm regime. The model is derived by applying Gauss's law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.     

High quality GaAs qrowth by MBE on Si using GeSi buffers and prospects for space photovoltaics

III–V solar cells on Si substrates are of interest for space photovoltaics since this would combine high performance space cells with a strong, lightweight and inexpensive substrate. However, the primary obstacles blocking III–V/Si cells from achieving high performance to date have been fundamental material incompatibilities, namely the 4% lattice mismatch between GaAs and Si, and the large mismatch in thermal expansion coefficient. In this paper, we report on the molecular beam epitaxial (MBE) growth and properties of GaAs layers and single junction GaAs cells on Si wafers which utilize compositionally graded GeSi intermediate buffers grown by ultra‐high vacuum chemical vapor deposition (UHVCVD) to mitigate the large lattice mismatch between GaAs and Si. GaAs cell structures were found to incorporate a threading dislocation density of 0.9–1.5×10 cm⁻², identical to the underlying relaxed Ge cap of the graded buffer, via a combination of transmission electron microscopy, electron beam induced current, and etch pit density measurements. AlGaAs/GaAs double heterostructures were grown on the GeSi/Si substrates for time‐resolved photoluminescence measurements, which revealed a bulk GaAs minority carrier lifetime in excess of 10 ns, the highest lifetime ever reported for GaAs on Si. A series of growths were performed to assess the impact of a GaAs buffer layer that is typically grown on the Ge surface prior to growth of active device layers. We found that both the high lifetimes and low interface recombination velocities are maintained even after reducing the GaAs buffer to a thickness of only 0.1 μm. Secondary ion mass spectroscopy studies revealed that there is negligible cross diffusion of Ga, As and Ge at the III–V/Ge interface, identical to our earlier findings for GaAs grown on Ge wafers using MBE. This indicates that there is no need for a buffer to ‘bury’ regions of high autodoping, and that either pn or np configuration cells are easily accommodated by these substrates. Preliminary diodes and single junction AlGaAs heteroface cells were grown and fabricated on the Ge/GeSi/Si substrates for the first time. Diodes fabricated on GaAs, Ge and Ge/GeSi/Si substrates show nearly identical I–V characteristics in both forward and reverse bias regions. External quantum efficiencies of AlGaAs/GaAs cell structures grown on Ge/GeSi/Si and Ge substrates demonstrated nearly identical photoresponse, which indicates that high lifetimes, diffusion lengths and efficient minority carrier collection is maintained after complete cell processing. Copyright © 2000 John Wiley & Sons, Ltd.     

Electrical properties of GeSi surface- and buried-channel p-MOSFETsfabricated by Ge implantation

The electrical properties of surface- and buried-channel p-MOSFETs containing strained GeSi heterostructures synthesized by high-dose Ge implantation and solid phase epitaxial growth have been investigated. Compared with Si control devices on the same chips, GeSi transistors exhibited improved performance: the channel hole mobility and linear transconductance was up to 18% higher for surface-channel GeSi transistors, and up to 12% higher for buried-channel GeSi p-MOSFETs, than for equivalent Si devices. Ion-beam synthesis of GeSi strained layers therefore offers an attractive means for realising improved device performance in conventional Si device structures     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

Investigation of poly-Si1-xGex for dual-gateCMOS technology

Poly-Si_1-xGe_x-gated MOS capacitors were fabricated with x varying from 0 to 0.5. NMOS and PMOS C-V characteristics were measured. Reduced poly-gate depletion effect (PDE) was observed in PMOS devices with increasing Ge mole fraction; while for NMOS, devices with a Ge content ~20% exhibit the least PDE. Higher active dopant concentration and reduced gate-depletion width for devices featuring less PDE were confirmed. Work function difference (Φ_MS) was found to decrease slightly in N⁺ films and significantly in P⁺ films as Ge content increases. The shift in Φ_MS for N⁺ poly-Si_1-xGe_x is negligible while it is -0.13 V for P⁺Si_0.8Ge_0.2 and -0.32 V for P⁺Si_0.5Ge_0.5. The reduction in energy bandgap (ΔE_g) was also determined to increase from 0 to 0.26 eV as Ge content increases from 0 to 50%. For deep submicron dual-gate CMOS application, the shift in Φ_MS should be minimized for low and symmetrical V_th as well as improved short-channel effect (SCE). A Ge content of ~20% therefore seems to offer the best tradeoff between SCE and PDE     

Opportunities and challenges for Ge CMOS – Control of interfacing field on Ge is a key (Invited Paper)

Ge CMOS is very attractive for the post size-scaled Si-CMOS. However, we have to tackle a number of challenges with regard to materials and their interface control. In this paper, we discuss gate stack formation and source/drain engineering, as well as their implications for the performance of n- and p-MOSFETs. Because the Ge interface is significantly degraded by the GeO desorption occurring at a relatively low temperature (～500 °C), it is very hard to control Ge gate stack formation by a simple thermal budget control. In addition, strong Fermi-level pinning at the Ge/metal interface is a big problem in source/drain engineering. After discussing ways to control this desorption and Fermi-level pinning at the interface in both p-FETs and n-FETs, we discuss our current status of both electron and hole mobilities.     

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (Φ_BN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low Φ_BN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300 K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.     

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOl devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.