一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路．BDD器件以电流模式的开关电流存储器为基本单元，具有符合二元判定图的两向通路的特点．用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路．给出了或门、异或门及四位加法器电路的例子，并使用HSPICE仿真器进行了仿真，验证了这种器件及其电路的正确性．     

BILCO: built in testing method for combinational logic circuits

The testing of digital logic circuits has become quite complex owing to miniaturisation and its associated increase in circuit function per unit area. Methods have been devised for testing ASIC products and, latterly, board level products. A new method (BILCO) is presented for probing asynchronous combinational logic circuits using a novel development of scan path principles     

Method for evaluation of transient-fault detection techniques

This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of injections that reproduce output scenarios of fault-affected combinational circuits. Furthermore, a detection technique is proposed and compared to state-of-the-art strategies by using the method presented herein. Results show the capabilities of all studied techniques, providing a rank in terms of their efficiencies in detecting transient faults induced in combinational logic circuits, and analyzing the situations in which soft errors are produced in memory elements.     

Propagation delay optimisation in multistage GaAs m.e.s.f.e.t. combinational logic circuits by use of dynamic programming

Propagation delays in multistage combinational logic circuits using GaAs metal-semiconductor field-effect transistors (m.e.s.f.e.t.s) are optimised subject to constraints on the overall power dissipation. Specific optimisation criteria are derived for 1-stage, 2-stage, and 3-stage combinational logic circuits. The results are evaluated with parameters of an existing process.     

判奇电路实现方法探讨

以三输入判奇电路设计为例,通过对其输出函数表达式的形式变换,分别采用多种门电路及译码器、数据选择器等74系列器件进行电路设计,给出了7种电路实现形式,并分析了各种电路实现的优缺点。此例说明了组合逻辑电路设计的灵活性及电路实现的多样性。所采用的设计方法对其他组合逻辑电路设计具有一定的启发与指导意义。     

Synthesis of multiple input-change hazard-free combinational switching circuits without feedback†

This paper deals with hazards on outputs of combinational circuits without feedback for multiple input changes. A procedure is given to decompose a Boolean function into a feedback free circuit. The procedure either gives a logic hazard-free circuit or shows that the Boolean function cannot be broken down into a feedback free circuit which is free of logic hazards for multiple input changes. The procedure proves that all multiple input change combinational circuits cannot be implemented without dynamic logic hazards with no internal feedback. The result is therefore considerably different than the single input change and multiple input change static logic hazard cases.     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

一款消除浮空点并自锁存的老化预测传感器

针对负偏置温度不稳定性引起的组合逻辑电路老化,提出了一款消除浮空点并自锁存的老化预测传感器。该传感器不仅可以预测组合逻辑电路老化,而且能够通过传感器内部的反馈来锁存检测结果,同时解决稳定性校验器在锁存期间的浮空点问题,其延时单元为可控型延时单元,可以控制其工作状态。使用HSPICE软件进行仿真,验证了老化预测传感器的可行性,可以适用于多种环境中且不会影响传感器性能。与同类型结构相比,该传感器的稳定性校验器能够对检测结果进行自锁存,使用的晶体管数量减少了约8%,平均功耗降低了约20%。     

CPLD实现雷达自动增益控制的优化

复杂的可编程逻辑器件可以完成较大规模的组合逻辑电路设计，提高系统的集成化。本文介绍了复杂可编程逻辑器件和电路设计的一般流程，以及数字自动增益控制电路的组成和采用CPLD设计的实现。     

Exact reliability analysis of combinational logic circuits

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed     

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V _DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.     

Redundancies and don't cares in sequential logic synthesis

The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions.In this article, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine.We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines. For each of the different classes of redundancies, we define don't care sets which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. We present systematic methods for the exploitation of sequential don't cares that correspond to sequences of vectors that never appear in cascaded or interacting sequential circuits. Using these don't care sets in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable lumped or interacting finite state machines. We present experimental results which indicate that medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times by exploiting these don't cares.     

Current-mode circuits for ternary-logic realisation

High-speed current-mode circuits for the realisation of ternary combinational logic expressions are described.     

Proposal of dual-powered superconducting logic circuits

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.     

Modeling for bridging faults in nMOS combinational circuits

A transistor level model that fully describes the logical behavior of a circuit in the presence of bridging faults is presented for the nMOS combinational circuits. The proposed model is suitable for the circuits having static enhancement/depletion (E/D) load. Thus, the model can be applied to circuits like pseudo nMOS and CMOS non-threshold-logic (NTL). The model employs a logic transistor function (LTF) to examine the behavior of such circuits. The LTF model developed earlier for stuck faults in nMOS circuits is extended for bridging faults. Algorithms that were developed for the stuck faults in pseudo nMOS combinational circuits can be applied to generate the test vectors for bridging faults.     

Determination of combinational logic circuit reliability through generation of fault diagnosis tests

This paper investigates the relationships between a given set of excitation vectors and the test sets for faults occuring in combinational circuits, in order to obtain new conditions for determining the redundant cubes of terminal states. The analysis presented is concluded with two new algorithms for the evaluation of combinational logic circuit reliability.     

Synthesis for logical initializability of synchronous finite-statemachines

Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, X) simulator. In practice, commercial logic and fault simulators often require initialization under such a three-valued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensure the logical initializability of synchronous finite-state machines. The method includes both state assignment and combinational logic synthesis steps. It is shown that a previous approach to synthesis-for-initializability, which uses a constrained state assignment method, may produce uninitializable circuits. Here, a new state assignment method is proposed that is guaranteed correct. Furthermore, it is shown that combinational logic synthesis also has a direct impact on initializability; necessary and sufficient constraints on combinational logic synthesis are proposed to guarantee that the resulting gate-level circuits are logically initializable. The above two synthesis steps have been incorporated into a computer-aided design tool, SALSIFY, targeted to both two-level and multilevel implementations     

基于重写规则法的形式验证技术

<正> 一、引言 验证逻辑设计正确性的传统方法是模拟(Simulation),然而随着数字电路规模和功能扩大,模拟方法已不能保证设计的正确性。与此相对,形式验证(formal verification)方法通过对电路结构的形式进行检查和比较来完成验证。它不需要模拟,因而,避开了模拟信号指数上升的问题。形式验证是一个静态分析,它比动态的逻辑模拟具有更大的潜力。 形式验证的一种方法是将其视为自动定理证明:已知一些公理和已成立的引理,证明某一表达式与另一表达式是等价的。美国Illinois技术研究所的A.S.Wojcik用AURA自动定理证明系统进行了逻辑设计的形式验证,AURA用归结原理作自动定理证明,由于归结法会产生大量子句,因此,证明的效率不是很高。     

FAOG:基于过滤技术和AOG的组合电路多故障诊断算法

本文提出了一种用于组合电路中的多故障诊断的新算法FAOG（Filtered AND／OR graphs）。此算法基于过滤技术和AOG图。其中过滤技术用来除去电路中的非可能致错部分，以减少所需处理的电路规模。AOG是与电路对应的AND／OR图，是改错的关键部分。此算法对于树状组合电路是完全自动的。对于普通组合电路是半自动的。它既解决了基于模拟的改错算法只能限定出错区域而不能告知如何诊断故障信息的局限性，也大大减轻了符号诊断法的内存爆炸问题。实验表明，这是一种快速高效的故障诊断方案，适用于多故障的组合电路。     

Latched CMOS differential logic (LCDL) for complex high-speed VLSI

A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL