Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support double-binary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 dB.     

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm² by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.     

Turbo码随机性交织器设计

深空测控中为获得较高的编码增益需要用到信道编译码技术。Turbo码是一种逼近香农限的高性能的信道编译码,其中,交织器的设计是影响Turbo码性能的关键因素之一。论述了交织器设计的基本准则,并详细介绍了3种常见的随机性交织器:伪随机交织器、S随机交织器和S改进型交织器的交织原理,对比分析了3种交织器的优缺点并给出了仿真结果。结果表明,交织器生成方式的不同将带来不同的Turbo码译码性能。     

分布式视频编码中符号Turbo码交织器的设计

分析了交织器在Turbo码中的作用,指出了现有的几种交织器的缺点.设计了两种新型的基于块交织的S随机交织器和基于伪随机交织的S随机交织器.仿真结果表明,与现有的几种交织器相比,这两种交织器在Turbo码译码迭代次数及延时方面性能更好,更适合于分布式视频编码系统.     

Turbo码中交织器的作用及设计

分析了Turbo码的编译码方案,然后讨论了交织器在Turbo码设计方面的重要作用,给出了几种交织器的实现方法,并模拟分析了其性能。     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

TURBO码中的交织器设计及其改进

Turbo码是近年来提出的一种信道编码.该系统在编码时采用并行的反馈系统卷积码(RSC).在编码的同时,对原始信息和经过交织(interleave)乱序的信息进行编码.Turbo码的解码一般采用软输入软输出解码器(SISO).其解码算法主要有SOVA、MAP以及改进的LOGMAN算法.Turbo码的编解码中,交织器的性能是一个关键问题.文章对交织器的设计和各种交织器的性能进行了探讨,并提出了一种易于硬件实现的交织器设计方法.     

A Parallel Turbo Decoder Based on Recurrent Neural Network

Wireless Personal Communications - A neural network-based decoder, based on a long short-term memory (LSTM) network, is proposed to solve the problem that large decoding delay and performance...     

Turbo码高速译码器设计

Turbo码具有优良的纠错性能,被认为是最接近香农限的纠错码之一,并被多个通信行业标准所采用。Turbo码译码算法相比于编码算法要复杂得多,同时其采用迭代译码方式,以上2个原因使得Turbo码译码器硬件实现复杂,而且译码速度非常有限。从Turbo码高速译码器硬件实现出发,介绍Turbo码迭代译码的硬件快速实现算法以及流水线译码方式,并介绍利用Altera的Flex10k10E芯片实现该高速译码器硬件架构。测试和仿真结果表明,该高速译码器具有较高的译码速度和良好的译码性能。     

基于FPGA的Turbo码译码器的设计

主要论述了一种基于FPGA的Turbo码译码器的设计。首先简单介绍了编码器和交织器的原理;然后介绍了基于Max-Log-MAP算法的译码器原理,对分量译码器做了详细论述,给出了各子模块原理和ModelSim仿真图形;最后给出了系统仿真的误码率图形。     

Modified Collision-Free Interleavers for High Speed Turbo Decoding

Inter-window shuffle (IWS) interleavers are a class of collision-free (CF) interleavers that have been applied to parallel turbo decoding. In this paper, we present modified IWS (M-IWS) interleavers that can further increase turbo decoding throughput only at the expense of slight performance degradation. By deriving the number of M-IWS interleavers, we demonstrate that the number is much smaller than that of IWS interleavers, whereas they both have a very simple algebraic representation. Further, it is shown by analysis that under given conditions, storage requirements of M-IWS interleavers can be reduced to only 368 storage bits for variable interleaving lengths. In order to realize parallel outputs of the on-line interleaving addresses, a low-complexity architecture design of M-IWS interleavers for parallel turbo decoding is proposed, which also supports variable interleaving lengths. Therefore, the M-IWS interleavers are very suitable for the turbo decoder in next generation communication systems with the high data rate and low latency requirements.     

Turbo译码器的低功耗设计

为了降低Turbo码译码器的功耗,作者介绍了一种利用对迭代次数的优化和关闭闲置状态下的译码器来降低功耗的方案;由于在SISO中,存放分支路径值以及前向路径状态值的储存体在功率的消耗上约占整个Turbo译码器功耗的70%,作者提出自己的方案,通过增加逻辑电路来减小储存体的大小从而降低译码器的功耗.实验结果表明修改后的方案可以降低比传统方案约12%的功耗.可见,在低功耗设计中抓住功率的消耗主体尤为关键.     

基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

基于FPGA的Turbo译码交织器设计

介绍了一种Turbo译码交织器的现场可编程门阵列（Field Programmable Gate Array，FPGA）硬件实现方案，将交织算法的软件编程和FPGA内部的硬件存储块相结合，有效地降低了译码器的硬件实现复杂度，减小了译码延时，并且给出了具体的译码器内交织器FPGA实现原理框图。     

A Low Complexity Algorithm for Generating Turbo Code s-Random Interleavers

In this paper we present a low complexity algorithm based on the bubble search sorting method that can be used to generate Turbo code interleavers that fulfill several criteria like spreading (s-randomness), code matched criteria and even the odd–even property for Turbo Trellis Coded Modulation. Simulation results show that for \(s < \sqrt{N/2}\) the algorithm is extremely efficient for short to medium interleaver lengths.     

Design and Optimization of an HSDPA Turbo Decoder ASIC

The turbo decoder is the most challenging component in a digital HSDPA receiver in terms of computation requirement and power consumption, where large block size and recursive algorithm prevent pipelining or parallelism to be effectively deployed. This paper addresses the complexity and power consumption issues at algorithmic, arithmetic and gate levels of ASIC design, in order to bring power consumption and die area of turbo decoders to a level commensurate with wireless application. Realized in 0.13  mum CMOS technology, the turbo decoder ASIC measures 1.2 mm² excluding pads, and can achieve 10.8 Mb/s throughput while consuming only 32 mW.     

跳频系统下Turbo编译码器的设计

在介绍Turbo码编译码原理基础上,针对特定跳频系统,设计了一种Turbo编译码方案。详细论述了该方案中编译码器的设计、建模和仿真过程。该方案中采用MAX-LOG-MAP的迭代译码算法,仿真验证了译码器采用6次迭代可以在保证抗干扰性能的前提下,面向硬件实现计算量适中。因此,该方法具有一定的工程应用价值。     

码率可配置Turbo译码器设计与实现

本文介绍了码率可配置 Turbo 译码器的 FPGA 设计与实现。可配置 Turbo 译码器可灵活支持 1/3、1/6、1/10 三种码率,减少了器件使用规模和资源,并支持固定迭代次数译码和动态迭代译码。码率可配置 Turbo 译码器最终在 Xilinx 公司的 XC7K325T-2FFG900I 芯片上实现。     

A Hybrid Decoder for Block Turbo Codes

We propose a novel iterative decoder for block turbo codes (BTCs). The proposed decoder combines soft-input/softoutput (SISO) and hard-input/hard-output (HIHO) constituent decoders in order to obtain better error performance and reduce the computational complexity compared to classical BTC decoders. We show that the new decoder, called ?hybrid decoder?, offers a better complexity/performance tradeoff than a classical BTC decoder.