Thermally stable Ge/Ag/Ni Ohmic contact for InAlAs/InGaAs/InP HEMTs

Excellent annealed ohmic contacts based on Ge/Ag/Ni metallization have been realized in a temperature range between 385 and 500/spl deg/C, with a minimum contact resistance of 0.06 /spl Omega//spl middot/mm and a specific contact resistivity of 2.62 /spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ obtained at an annealing temperature of 425/spl deg/C for 60 s in a rapid thermal annealing (RTA) system. Thermal storage tests at temperatures of 215 and 250/spl deg/C in a nitrogen ambient showed that the Ge/Ag/Ni based ohmic contacts with an overlay of Ti/Pt/Au had far superior thermal stabilities than the conventional annealed AuGe/Ni ohmic contacts for InAlAs/InGaAs high electron mobility transistors (HEMTs). During the storage test at 215/spl deg/C, the ohmic contacts showed no degradation after 200 h. At 250/spl deg/C, the contact resistance value of the Ge/Ag/Ni ohmic contact increased only to a value of 0.1 /spl Omega//spl middot/mm over a 250-h period. Depletion-mode HEMTs (D-HEMTs) with a gate length of 0.2 /spl mu/m fabricated using Ge/Ag/Ni ohmic contacts with an overlay of Ti/Pt/Au demonstrated excellent dc and RF characteristics.     

Fabrication of niobium titanium nitride thin films with high superconducting transition temperatures and short penetration lengths

We report a systematic study of the superconducting and normal state properties of reactively sputtered Nb/sub 0.62/Ti/sub 0.38/N thin films deposited on thermally oxidized Si wafers. The superconducting transition temperature (T/sub c/) was found to increase from 12 K for films prepared on unheated substrates to over 16 K for films prepared on substrates maintained at 450/spl deg/C. A Nb buffer layer was found to improve T/sub c/ by /spl sim/0.5 K for growths at lower substrate temperatures. The films fabricated at 450/spl deg/C have an amply smooth surface (1.5/spl plusmn/0.25 nm root mean square roughness), a sufficiently high T/sub c/, and sufficiently small penetration depth (200/spl plusmn/20 nm at 10 K) to be useful as ground planes and electrodes for current-generation 10 K rapid single-flux quantum circuit technology.     

A two-terminal IC temperature transducer

A bipolar monolithic IC temperature transducer with an operating temperature range of -125/spl deg/C to +200/spl deg/C has been designed, fabricated, and tested. The two-terminal device, which is fabricated using laser trimmed thin-film-on-silicon technology, is a calibrated temperature dependent current source with an average output impedence of 10 M/spl Omega/ over the 3.5-V to 30-V range of input voltage. Overall absolute accuracies of /spl plusmn/0.5/spl deg/C from -75/spl deg/C to +150/spl deg/C have been achieved on a scale of 1 /spl mu/A/K under optimum operating conditions.     

Controllability of novel Sn/sub 0.95/Au/sub 0.05/ microbumps using interlaminated tin and gold layers for flip-chip interconnection

A flip-chip interconnection technology using novel lead-free solder microbumps with a balling temperature as low as 220 /spl deg/C is presented. Controllability of newly developed Sn/sub 0.95/Au/sub 0.05/ microbumps has been examined experimentally. By varying the bump volume and the diameter of the wettable bump electrodes, Sn/sub 0.95/Au/sub 0.05/ microbumps with heights from 11 /spl mu/m to 37 /spl mu/m were successfully fabricated with a standard deviation of 1.5 /spl mu/m. The deviation of on-chip CPW impedance from 50 /spl Omega/ was lower than 10% for nonmetallization motherboard. The smaller bumps exhibited a better performance since the degradation of reflection properties is ascribed to the bump capacitance, which was estimated 10-20 fF. Because of high process yield and good performance, the flip-chip bonding using Sn/sub 0.95/Au/sub 0.05/ microbumps of the order of 20 /spl mu/m in height may be advantageous for W-band interconnection of InP- or GaAs-based devices.     

Effect of CVD-SiO/sub 2/ film on reliability of GaAs MESFET with Ti/Pt/Au gate metal

The effect of CVD-SiO/sub 2/ films on the reliability of GaAs MESFET with Ti/Pt/Au gate metal was investigated. It was found that the mean time to failure (MTTF) of MESFET with 350/spl deg/C-depositied SiO/sub 2/ was only about one-seventh of that of the ones with 440/spl deg/C-SiO/sub 2/. It was also found that, in the storage test at 300/spl deg/C for 24 hours, diffusion of Pt into GaAs was accelerated when the SiO/sub 2/ deposition temperature was lower than 380/spl deg/C. FT-IR spectra indicated that the lower deposition temperature leads to a higher concentration of the residual hydrogen in SiO/sub 2/. Thermal differential spectrometry (TDS) demonstrated that hydrogen in SiO/sub 2/ could migrate even below 300/spl deg/C. In conclusion, the residual hydrogen in SiO/sub 2/ causes the degradation phenomena.     

Large-value monolithic resistors for micropower integrated circuits

The minimum power dissipation of micropower integrated circuits is often limited by the availability of large-value monolithic resistors. Two major types of field-effect resistor structures are examined and an analysis of the primary factors that determine sheet resistance and parasitic capacitance is presented. Resistor tolerance, linearity, and temperature coefficient are briefly discussed. It is shown that resistors with sheet resistances greater than 50 k/spl Omega///spl square/ and parasitic capacitances less than 0.002 pF/k/spl Omega/ can be readily fabricated in a monolithic structure.     

Printed microinductors on flexible substrates for power applications

A low-profile microinductor was fabricated on a copper-clad polyimide substrate where the current carrying coils were patterned from the existing metallization layer and the magnetic core was printed using a magnetic ceramic-polymer composite material. Highly loaded ferrite-polymer composite materials were formulated, yielding adherent films with 4/spl pi/M/sub s//spl ap/3900 G at +5000 Oe applied DC field. These composite magnetic films combine many of the superior properties of high temperature ceramic magnetic materials with the inherent processibility of polymer thick films. Processing temperatures for the printed films were between 100/spl deg/C and 130/spl deg/C, facilitating integration with a wide range of substrates and components. The quality factor of the microinductor was found to peak at Q=18.5 near 10 MHz, within the optimal frequency range for power applications. A flat, nearly frequency independent inductance of 1.33 /spl mu/H was measured throughout this frequency range for a 5 mm/spl times/5 mm component, with a DC resistance of 2.6 /spl Omega/ and a resonant frequency of 124 MHz. The combination of printed ceramic composites with organic/polymer substrates enables new methods for embedding passive components and ultimately the integration of high Q inductors with standard integrated circuits for low profile power electronics.     

SiC thin-film Fabry-Perot interferometer for fiber-optic temperature sensor

Polycrystalline SiC grown on single-crystal sapphire substrates have been investigated as thin-film Fabry-Perot interferometers for fiber-optic temperature measurements in harsh temperatures. SiC-based temperature sensors are compact in size, robust, and stable at high temperatures, making them one of the best choices for high temperature applications. SiC films with thickness of about 0.5-2.0 /spl mu/m were grown at 1100/spl deg/C by chemical vapor deposition (CVD) with trimethylsilane. The effect of operating temperature on the shifts in resonance minima, /spl Delta//spl lambda//sub m/, of the SiC/sapphire substrate has been measured in the visible-infrared wavelength range. A temperature sensitivity of 1.9/spl times/10/sup -5///spl deg/C is calculated using the minimum at /spl sim/700 nm. Using a white, broadband light source, a temperature accuracy of /spl plusmn/3.5/spl deg/C is obtained over the temperature range of 22/spl deg/C to 540/spl deg/C.     

Fabrication of MOD-derived YBCO films on [001]LaAlO/sub 3/ and their application to /spl lambda//4 CPW SIR BPFs

Chemically derived epitaxial thin films of YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// (YBCO) are fabricated on [001]LaAlO/sub 3/ substrates by the metalorganic-deposition (MOD) process, which has advantages of high quality, nonvacuum, low-cost, and large-scale production of high-T/sub c/ superconducting films. The MOD-derived YBCO films have a sharp transition at the critical temperature (90.4 K) and a high-quality film with a surface resistance of 0.13 m/spl Omega/ (30 K, 9.98 GHz) is obtained. As a microwave application, simple and compact bandpass filters (BPFs) using /spl lambda//4 coplanar-waveguide. stepped-impedance resonators are demonstrated on the YBCO films. A two-stage Chebyshev BPF of center frequency of 5.731 GHz, bandwidth of 135 MHz, and insertion loss of 0.29 dB with little input power dependency in a power range less than 10 dBm is realized on the film.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

An accurate integrated voltage-to-current converter

Presents a monolithic integrated differential voltage-to-current converter. The transconductance of the converter is determined accurately by one external resistor. A total error in the conversion factor as low as /spl plusmn/0.5 percent is obtained by using composite transistors and by using the mutual equality of integrated resistors. The transconductance has a nonlinearity of 0.02 percent and a temperature coefficient of 4/spl times/10/SUP -5///spl deg/C. The output impedance is 5 M/spl Omega/. The voltage-to-current converter is a versatile building block. It can be applied as an instrumentation amplifier, a universal current mirror or current follower, etc.     

Temperature-dependent I-V characteristics of organic-inorganic heterojunction diodes

In this paper, heterojunctions were fabricated by employing p-type Si and thin films of poly-N-epoxipropylcarbazole (PEPC) doped with tetracyanoquinodimethane (TCNQ). The PEPC films were grown on Si wafers at room temperature but with different gravity (g) conditions:-1, 123, 277, and 1107g. Current-voltage (I-V) characteristics of the grown hybrid structures were evaluated as a function temperature (T) ranging from 20/spl deg/C to 60/spl deg/C. It was found that all samples are p-p isotype heterojunctions and the junctions fabricated at a high value of g, i.e., at 277 and 1107 g, showed reversible rectifying properties as a function of device temperature. Whereas the behavior of devices fabricated at 123 and 1 g were rectifying at room temperature, but became almost nonconductive after treating the samples at 60/spl deg/C. Rectification ratio, threshold voltage, reverse saturation current, and junction resistance of the fabricated junctions were evaluated at different temperatures. At T=60/spl deg/C, the devices grown at 1107 g exhibited rectification ratio less than unity which may be attributed to the switching of the depletion at the interface. This has been explained by assuming the generation of carriers are at elevated temperatures in the organic film, and their subsequent emission from the organic to the inorganic side of the heterojunction.     

1330 V, 67 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC(0001) RESURF MOSFET

Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented.     

Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250/spl deg/C to 280/spl deg/ C

Amorphous-silicon (a-Si) thin-film transistors (TFTs) were fabricated on a free-standing new clear plastic substrate with high glass transition temperature (T/sub g/) of >315/spl deg/ C and low coefficient of thermal expansion of <10 ppm/ /spl deg/ C. Maximum process temperatures on the substrates were 250/spl deg/C and 280/spl deg/C, close to the temperatures used in industrial a-Si TFT production on glass substrates. The first TFTs made at 280/spl deg/C have dc characteristics comparable to TFTs made on glass. The stability of the 250/spl deg/C TFTs on clear plastic is approaching that of TFTs made on glass at 300/spl deg/C-350/spl deg/C. TFT characteristics and stability depend only on process temperature and not on substrate type.     

5 V temperature regulated voltage reference

A 5 V internally temperature regulated voltage reference integrated circuit, which achieves 0.3 ppm//spl deg/C TC over the temperature range -55/spl deg/C to 125/spl deg/C, is described. It is built using a buried zener reference in a dielectrically isolated complementary bipolar process which employs laser trimmed NiCr thin film resistors and a high thermal resistance epoxy die attach.     

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.     

Layer-by-layer nanoarchitecture of ultrathin films of PEDOT-PSS and PPy to act as hole transport layer in polymer light emitting diodes and polymer transistors

In this paper, we report a controlled architectural growth of ultrathin films of conducting polymers via layer-by-layer (L-b-L) self-assembly with poly(3, 4-ethylenedioxythiophene), poly(styrenesulfonate) (PEDOT-PSS), and polypyrrole (PPy) as alternating layers. A typical step of the film growth was 2.3/spl plusmn/0.1nm for every other bilayer. Linear growth of thin films has been observed by annealing each layer, while super-assembly was observed without annealing. The conductivities obtained range from 0.037S/cm at room temperature to 0.13S/cm at 120/spl deg/C. The improved conductivity may be attributed to either the increase in mobility of charged carriers due to less carrier scattering in the self-assembled layer, or the increased inter-chain hopping between two polymers due to closely packed polymer-chains. The charged carriers in the hole transport layer (HTL) increase the recombination rate of electrons and holes in the electroluminescent layer thus increasing the external quantum efficiency of the polymer light emitting diodes (PLEDs). Polymer field effect transistors have been fabricated using L-b-L assembled PEDOT-PSS and PPy. Polymer field-effect transistors (PFETs) with a number of different gate lengths were used to obtain source/drain contact resistance and channel mobility. The overall mobility from the L-b-L assembled PEDOT/PPy is calculated to be 8.8/spl times/10/sup -3/cm/sup 2//Vs at the linear regime. This mobility is five times higher than the spin coated device in linear regime. The I/sub on//I/sub off/ current ratio is 210. Thus confinements of holes in L-b-L assembled conducting polymer films improve the overall performance of polymer thin film transistors.     

An electro-thermal model for metal-oxide-metal antifuses

In this paper, a complete electro-thermal analysis is presented for the metal-oxide-metal antifuses. The application of the Wiedemann-Franz Law and the thin film effect on thermal and electrical conductivities of metal films were also discussed. Several key parameters for tungsten-oxide-tungsten antifuse were extracted. The reaction temperature between tungsten and oxide was estimated to be around 1300/spl deg/C. The core resistivity was found to be around 250 /spl mu//spl Omega//spl middot/cm. This model can be readily extended to the other metal-dielectric-metal systems.<>     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

Development of screen-printed silicon solar cells with high fill factors on 100 /spl Omega//sq emitters

High-quality DuPont screen-printed Ag contacts were achieved on high sheet-resistance emitters (100 /spl Omega//sq) by rapid alloying of PV168 Ag paste. Excellent specific contact resistance (/spl sim/1 m/spl Omega/-cm/sup 2/) in conjunction with high fill factor (FF) (0.775) were obtained on 100 /spl Omega//sq emitters by a 900/spl deg/C spike firing of the PV168 paste in a belt furnace. The combination of the alloying characteristics of the PV168 Ag paste and optimized single-step rapid low-thermal budget firing resulted in a cost-effective manufacturable process for high-efficiency Si solar cells. In addition, the co-fired 100 /spl Omega//sq cell showed a noticeable improvement of /spl sim/0.5% in absolute efficiency over a conventional co-fired 45 /spl Omega//sq emitter cell. Lighter doping in the 100 /spl Omega//sq emitter cell resulted in better blue-response compared to the conventional cell, contributing to /spl sim/1.3 mA/cm/sup 2/ improvement in short-circuit current. Improved surface passivation on 100 /spl Omega//sq emitter cell resulted in additional 0.6 mA/cm/sup 2/ increase in J/sub sc/, 15-mV higher V/sub oc/, and a 0.6% increase in absolute cell efficiency. Front grid design optimization resulted in a FF of 0.780, and a further improvement in cell efficiency to reach 17.4%.