软件体系结构的性能评价研究

介绍了软件体系结构的形式化描述方法-化学抽象机(ChemicalAbstractMachine,CHAM),总结了队列网络模型(QueueingNetworkModel,QNM)及其产生过程的特点。基于队列网络模型,由化学抽象机中形式化描述的软件体系结构规约,导出了一种性能评价模型。其目的是提供一个测量集,在高抽象层次上比较两个或更多候选软件体系结构的性能。最后,以多相编译器为例,具体阐述了这种性能评价。     

Brain Derived Vision Algorithm on High Performance Architectures

Even though computing systems have increased the number of transistors, the switching speed, and the number of processors, most programs exhibit limited speedup due to the serial dependencies of existing algorithms. Analysis of intrinsically parallel systems such as brain circuitry have led to the identification of novel architecture designs, and also new algorithms than can exploit the features of modern multiprocessor systems. In this article we describe the details of a brain derived vision (BDV) algorithm that is derived from the anatomical structure, and physiological operating principles of thalamo-cortical brain circuits. We show that many characteristics of the BDV algorithm lend themselves to implementation on IBM CELL architecture, and yield impressive speedups that equal or exceed the performance of specialized solutions such as FPGAs. Mapping this algorithm to the IBM CELL is non-trivial, and we suggest various approaches to deal with parallelism, task granularity, communication, and memory locality. We also show that a cluster of three PS3s (or more) containing IBM CELL processors provides a promising platform for brain derived algorithms, exhibiting speedup of more than 140 × over a desktop PC implementation, and thus enabling real-time object recognition for robotic systems.     

未来测试系统结构

在测试领域大量测试系统结构的存在使选择很易混淆,为此,总结了现存测试系统结构(GPIB、PC、VXI和PXI)的特点,并提出了一种新的基于LAN的测试系统结构.对各种测试系统结构的价格、通道数、尺寸、I/O速度和适应性等进行了比较,其目的是为未来的应用中提供最有效的测试系统.     

Software Architectures and Coordination Models

Coordination models and Software Architectures are strictly related but only a little attention has been paid to their integration. What we propose in this paper is an approach to trace coordination requirements from their definition to the low level specification. The UML Unified Process is extended to gain this objective and the theory is applied to a case study.     

Optical multiplexing techniques for photonic Clos networks in High Performance Computing Architectures

Future high-performance computing (HPC) architectures will consist of whole parallel computing systems integrated on chip-level and boards mounted with lots of computing chips and chip-external main memory. Photonic networks on board and photonic network on chips (NoCs) offer the potential to fulfill the high bandwidth requirements in such systems. In addition they need less power, offer better EMC capabilities and can reduce cabling effort compared to electronic networks. Due to their non-blocking property Clos networks are frequently used in HPC architectures. Therefore we investigated how a photonic on-board Clos network can be realized using Coarse Wavelength-Division-Multiplexing (CWDM) techniques with state-of-the art components based on fiber technology. In addition we present a new photonic Clos NoC architecture based on Wavelength Interchanging (WI) elements, optical waveguide structures, mode-locked laser sources, nanophotonic microrings and passive optical deflection elements to reduce the number of switches. We discuss the benefits and drawbacks for using different optical technologies for such an architecture.     

Network Architectures and Performance

The capability of networks to handle various forms of communications traffic and to interconnect is based on several network characteristics, most important, capacity and utilization. A review of available network architectures and their abilities to handle increasing user demand while maintaining reliability in a bandwidth-intensive environment helps sort out today's maze of networking options.     

高性能处理系统的软硬件协同设计研究

x86是目前应用最广泛的复杂指令(CISC)系统,对大量非典型特性进行支持,从而花费大量硬件资源.而非典型特性的支持往往会影响典型功能的效率,不利于硬件资源的优化配置,限制处理系统性能的提升.本文首先分析了x86指令集及x86程序的固有特性,进而提出了一种基于RISC超标量处理系统核心的软硬件协同设计的实现方案.新处理系统的面积仅为采用硬件译码设计的x86处理系统的78.3%,性能达到采用硬件译码设计的x86处理系统的90.6%以上,并有较大的提升空间.     

Performance Analytic Models and Analyses for Workflow Architectures

The design and implementation of a workflow management system is typically a large and complex task. Decisions need to be made about the hardware and software platforms, the data structures, the algorithms, and network interconnection of various modules utilized by various users and administrators. These decisions are further complicated by requirements such as flexibility, robustness, modifiability, availability, performance, and usability. As the size of workflow systems increases, organizations are finding that the standard server/client architectures, and off-the-shelf solutions are not adequate. We can further see that in the future, very large-scale workflow systems (VLSW) will become more complex, and more prevalent. Thus, one further requirement is an emphasis of this document: scalability. For the purposes of our scalable workflow investigations, we describe a framework, a taxonomy, a model, and a methodology to investigate the performance of various workflow architectures as the size of the system (number of workcases) grows very large.First, this paper presents a novel workflow architectural framework and taxonomy. We survey some example current workflow products and research prototype systems, illustrating some of the taxonomical categories. In fact, most current workflow architectures fall into only one of the many categories of this taxonomy: the centralized server/client category. The paper next explains a performance analysis methodology useful for exploring this taxonomy. The methodology deploys a layered queuing model, and performs mathematical analysis on this model using a modified MOL (method of layers) combined with a linearization algorithm. Finally, the paper utilizes this methodology to compare and contrast the various architectural categories, providing interesting results about performance as the number of workcases increases. Our analytic results suggest that (a) for VLSW performance determination, software architecture is as important as hardware architecture, and (b) alternatives to the client server architecture provide significantly better scalability.     

新型软件体系结构研究

软件体系结构的研究成果显著,已经总结和提炼了一批经典的软件体系结构风格,并得到了广泛应用。但不能有效满足和适应当前日益复杂和千变万化的需求,需要适时趣从理论上作更深入的研究和提出一些新的软件体系结构风格来支撑。本文对软件体系结构研究的新动向和新兴的体系结构风格进行了总结和比较,并就当前的研究现状给出了几点思考,指出层级理论是构建复杂软件体系的基本原则,模型比语言更具有描述大型复杂系统的优势。     

超级计算机体系结构及应用情况

本文概述了当今超级计算机体系结构类型及特点,考察了国外超级计算机在气象、核模拟、CFD、生物信息学和医学、天体物理学等典型应用领域的应用情况,分析了超级计算机体系结构与应用领域之间的关系。     

Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures

It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On the other hand, chip-multiprocessors (CMP) that integrate several processor cores in a single chip are nowadays the best alternative to more efficient use of the increasing number of transistors that can be placed in a single die. Hence, it is necessary to design new techniques to deal with these faults to be able to build sufficiently reliable chip multiprocessors (CMPs). In this work, we present a coherence protocol aimed at dealing with transient failures that affect the interconnection network of a CMP, thus assuming that the network is no longer reliable. In particular, our proposal extends a token-based cache coherence protocol so that no data can be lost and no deadlock can occur due to any dropped message. Using GEMS full system simulator, we compare our proposal against TokenCMP. We show that in absence of failures our proposal does not introduce overhead in terms of increased execution time over TokenCMP. Additionally, our protocol can tolerate message loss rates much higher than those likely to be found in the real world without increasing execution time more than 15 percent.     

高性能局域网监测软件的设计

研究设计了一种利用遵循SNMP协议的高效软件MRTG来获取局域网网络节点状态信息的有效方法,并将流量负载以包括PNG格式图像的HTML文档方式提供给用户,以非常直观的形式显示流量负载,以便查明设备和网络的性能问题。     

高性能感应电机电流控制方法分析与比较

简要地综述了高性能感应电机电流控制技术的最新进展。重点分析了以控制理论为基础的基于模型的方法,主要包括滞环电流控制、比例积分控制、有限拍控制。介绍了它们的基本工作原理,讨论了它们目前存在的不足之处以及针对这些问题近期的研究工作提出的解决办法。同时也对基于神经网络和模糊逻辑的智能控制策略进行了分析,它们为电流控制的发展开拓了新的思路。最后系统地比较了各种方法的控制性能并且初步探讨了该领域今后的发展趋势。     

Modelling Dynamic Software Architectures using Typed Graph Grammars

Several recent research efforts have focused on the dynamic aspects of software architectures providing suitable models and techniques for handling the run-time modification of the structure of a system. A large number of heterogeneous proposals for addressing dynamic architectures at many different levels of abstraction have been provided, such as programmable, ad-hoc, self-healing and self-repairing among others. It is then important to have a clear picture of the relations among these proposals by formulating them into a uniform framework and contrasting the different verification aspects that can be reasonably addressed by each proposal. Our work is a contribution in this line. In particular, we map several notions of dynamicity into the same formal framework in order to distill the similarities and differences among them. As a result we explain different styles of architectural dynamisms in term of graph grammars and get some better insights on the kinds of formal properties that can be naturally associated to such different specification styles. We take a simple automotive scenario as a running example to illustrate main ideas.     

Efficient Implementations of Software Architectures via Partial Evaluation

The notion of flexibility (that is, the ability to adapt to changing requirements or execution contexts) is recognized as a key concern in structuring software, and many architectures have been designed to that effect. However, the corresponding implementations often come with performance and code size overheads. The source of inefficiency can be identified to be in the loose integration of components, because flexibility is often present not only at the design level but also in the implementation. To solve this flexibility vs. efficiency dilemma, we advocate the use of partial evaluation, which is an automated technique to produce efficient, specialized instances of generic programs. As supporting case studies, we consider several flexible mechanisms commonly found in software architectures: selective broadcast, pattern matching, interpreters, software layers, and generic libraries. Using Tempo, our specializer for C, we show how partial evaluation can safely optimize implementations of those mechanisms. Because this optimization is automatic, it preserves the original genericity and extensibility of the implementation.     

Software Architectures for Reducing Priority Inversion and Non-determinism in Real-time Object Request Brokers

There is increasing demand to extend Object RequestBroker (ORB) middleware to support distributed applications withstringent real-time requirements. However, conventional ORB implementations,such as CORBA ORBs, exhibit substantial priority inversion andnon-determinism, which makes them unsuitable for applicationswith deterministic real-time requirements. This paper providestwo contributions to the study and design of real-time ORB middleware.First, it illustrates empirically why conventional ORBs do notyet support real-time quality of service. Second, it evaluatesconnection and concurrency software architectures to identifystrategies that reduce priority inversion and non-determinismin real-time CORBA ORBs. The results presented in this paperdemonstrate the feasibility of using standard OO middleware likeCORBA to support certain types of real-time applications overthe Internet.