一种新的等离子体边缘损伤的测量方法

在等离子体刻蚀多晶硅工艺中,栅边缘氧化层直接暴露在等离子体环境中,由于UV射线的作用栅边缘处将会产生损伤,这种损伤包含了大量的界面态和氧化层陷阱.文中讨论了等离子体边缘损伤与圆片位置关系、天线比之间的关系及它们对器件长期可靠性的影响,并使用了低频局部电荷泵技术.测量的结果包含了损伤产生的快、慢界面态和氧化层陷阱的信息,可以较好地测量工艺中产生的栅边缘损伤,为评估薄栅MOSFET的栅边缘损伤提供了一种简单快捷的方法.     

TDDB击穿特性评估薄介质层质量

与时间相关电介质击穿(TDDB)测量是评估厚度小于20nm薄栅介质层质量的重要方法.氧化层击穿前,隧穿电子和空穴在氧化层中或界面附近产生陷阱、界面态,当陷阱密度超过临界平均值 _bd时,发生击穿.击穿电量Q_bd值表征了介质层的质量.Q_bd值及其失效统计分布与测试电流密度、电场强度、温度及氧化层面积等有定量关系.TDDB的早期失效分布可以反映工艺引入的缺陷.TDDB可以直接评估氧化、氮化、清洗、刻蚀等工艺对厚度小于10nm的栅介质质量的影响.它是硅片级评估可靠性和预测EEPROM擦写次数的重要方法.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究.研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化.应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加,击穿电荷减少,也会造成关态漏泄漏电流的退化.栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生.热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动,这解释了源区一侧栅氧化层损伤的产生原因.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

含N超薄栅氧化层的击穿特性

研究了含N超薄栅氧化层的击穿特性.含N薄栅氧化层是先进行900C干氧氧化5min,再把SiO2栅介质放入1000C的N2O中退火20min而获得的,栅氧化层厚度为10nm.实验结果表明,在栅介质中引入适量的N可以明显地起到抑制栅介质击穿的作用.分析研究表明,N具有补偿SiO2中O3 Si@和Si3 Si@等由工艺引入的氧化物陷阱和界面陷阱的作用,从而可以减少初始固定正电荷和Si/SiO2界面态,因此提高了栅氧化层的抗击穿能力.     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

电荷泵技术在CMOS工艺中的应用研究

随着CMOS工艺的发展,栅介质层厚度不断减薄,而电源电压并没有等比例缩小,导致栅漏电流不断增大,测量界面态的传统方法受到限制。介绍了电荷泵技术在表征深亚微米和超深亚微米器件Si/SiO2界面特性方面的应用;详述如何测量界面态和氧化层陷阱电荷的横向分布、能量分布和体陷阱深度分布;分析了当前电荷泵技术存在的问题和面临的挑战,提出通过抵消直接隧穿电流的影响,对电荷泵电流进行修正,使电荷泵技术能够在不同工艺下得到广泛应用。     

含氟超薄栅氧化层的抗击穿特性研究

对含 F超薄栅氧化层的击穿特性进行了实验研究。实验结果表明 ,在栅介质中引入适量的 F可以明显地提高栅介质的抗击穿能力。分析研究表明 ,栅氧化层的击穿主要是由于正电荷的积累造成的 ,F的引入可以对 Si/Si O2 界面和 Si O2 中的 O3 ≡ Si·与 Si3 ≡ Si·等由工艺引入的氧化物陷阱和界面陷阱进行补偿 ,从而减少了初始固定正电荷和 Si/Si O2 界面态 ,提高了栅氧化层的质量。研究结果表明 ,器件的击穿电压与氧化层面积有一定的依赖关系 ,随着栅氧化层面积的减小 ,器件的击穿电压增大。     

含N超薄栅氧化层的击穿特性

研究了含 N超薄栅氧化层的击穿特性 .含 N薄栅氧化层是先进行 90 0℃干氧氧化 5 m in,再把 Si O2 栅介质放入 10 0 0℃的 N2 O中退火 2 0 min而获得的 ,栅氧化层厚度为 10 nm.实验结果表明 ,在栅介质中引入适量的 N可以明显地起到抑制栅介质击穿的作用 .分析研究表明 ,N具有补偿 Si O2 中 O3≡ Si·和 Si3≡ Si·等由工艺引入的氧化物陷阱和界面陷阱的作用 ,从而可以减少初始固定正电荷和 Si/ Si O2 界面态 ,因此提高了栅氧化层的抗击穿能力     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Electrically active defects generated by MERIE and RIE-mode plasmas in thin SiO2-Si structures

The effect of both RIE and high-density nonuniform magnetically enhanced reactive ion etching (MERIE)-type plasmas on the properties of thin oxide (11–13 nm) MOS capacitors as well as FETs without gate has been investigated. The results reveal the vulnerability of the oxide and its interface with Si to the plasma process — the interface is much more sensitive. The creation of defects in the form of fixed oxide charge, bulk traps, slow states and interface states is found. The damage level is a function of both the discharge conditions (including plasma exposure time) and the initial Si-SiO₂ structure parameters, the plasma conditions having a priority impact. The damage process is very rapid particularly in the first seconds (up to 30 s) of plasma exposure. The effects become highly process dependent as the plasma time increases. The plasma induced defects degrade the inversion carrier mobility and change the dominant scattering mechanism in the inversion channel. The damage leads to an excess leakage current and decreases the breakdown fields. A strong linear correlation between plasma induced leakage current and plasma created positive charge is detected. It is established that the build-up damage depends on plasma nonuniformity, but the non uniformity is neither the only nor the dominating factor. The nature of process induced defects and the influence of plasma components are discussed. It is proposed that generated interface states are mainly attributed to VUV and ion bombardment, whereas the high values of positive oxide charge are due to the charging effect. The type of plasma induced defects (oxide traps or interface states) and the energy distribution of interface states strongly depend on the relative contribution (or domination) of the different plasma components.A room temperature annealing of MERIE-type plasma induced interface states is established. The reduction depends only on the starting postplasma treatment level of interface states and the effects responsible for this reduction take place very close to the Si-SiO₂ interface. (The fixed oxide charge is stable and it does not change at all.) The process seems to be controlled by moisture transport to the Si-SiO₂ interface.By means of X-ray photo electron spectroscopy it is found that 5 min exposure of thin thermal SiO₂ to N₂-RIE mode plasma causes structural modifications, which manifest only as a deterioration of oxide quality without actual nitration of the oxide. The presence of a small constant amount of SiO species through the oxide and a broadening of Si-SiO₂ interface region are detected.The nature of the electrically active plasma induced defects by both plasma processes — RIE and MERIE is equal — the bond defects in the oxide and at the interface: the oxide charge is associated with E′ centers and the interface states with P_b centers.     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

The electrostatic charging damage on the characteristics andreliability of polysilicon thin-film transistors during plasmahydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFT's) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFT's with different area of antennas were used to study the damages caused by electrostatic field     

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

Radiation-induced depassivation of latent plasma damage

Plasma treatments are widely used in microelectronic industry but they may leave some residual passivated damage in the gate oxides at the end of the processing. The plasma-induced damage can be amplified by metal interconnects (antenna) attached to the gate during the plasma treatments. Ionising radiation reactivates this latent damage, which produces enhanced oxide charge and Si/SiO₂ interface state density. Two CMOS technologies have been investigated, with 5 and 7 nm gate oxides. Threshold voltage shifts, transconductance decrease, and interface traps build-up are always larger for plasma damaged devices than for reference devices.     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors     

A new self-consistent modeling approach to investigating MOSFETdegradation

A modeling tool is presented that allows a complete analysis of a DC stress experiment without assuming the location and amount of trapped oxide charges and interface states. To describe the buildup of oxide damage, a semiempirical rate equation approach is outlined. A completely self-consistent calculation is presented of the time dependence of the DC stress experiment. This calculation monitors the amount and location of charges built up in the 2-D oxide region during the stress line. The model includes competing trap mechanisms such as the formation of interface states and fixed oxide traps. This permits consideration of n- and p-channel MOSFETs with the same model. The calculations are compared to DC stress measurements on n- and p-channel devices with gate lengths of 0.65 μm that are typical for 16-Mb DRAMs     

Recovery of the NBTI-Stressed Ultrathin Gate p-MOSFET: The Role of Deep-Level Hole Traps

Under a static negative-bias temperature stress, the negative threshold-voltage V_t shift (extracted from the dc current-voltage characteristic) of the direct-tunneling gate p-MOSFET is found to be substantially larger than that calculated based on the interface-state density measured using the charge-pumping method. Device-recovery characteristics from bipolar gate stress show that interface states alone cannot entirely account for the V_t shift, and indicate that a substantial number of positive oxide charges are also generated during stress. Stability of the increased V_t shift under a negative dc gate biasing and unipolar ac gate pulsing implies that these positive charges are deep-level hole traps with energy states above the Si conduction band edge. Because the defect states are outside the energy window of direct electron tunneling, their long relaxation time plays an important role in the slow recovery transient of the p-MOSFET     

Hot-carrier-induced degradation in reoxidized-nitrided-oxiden-MOSFETs under mixed AC-DC stressing

Reduced degradation rate can be observed for reoxidized-nitrided-oxide (RNO) n-MOSFETs under dynamic stressing versus the corresponding static stressing. A new degradation mechanism is proposed in which trapped holes in gate oxide are neutralized by the hot-electron injection, with no significant generation of interface states because of the hardening on the Si-SiO₂ interface by nitridation/reoxidation steps. The RNO device degradation during AC stressing arises mainly from the charge trapping in the gate oxide rather than the generation of interface states. Moreover, the AC-stressed RNO devices are significantly inferior to the fresh RNO devices in terms of DC stressing, possibly due to lots of neutral electron traps in the gate oxide resulting from the AC stressing