应用于SAR ADC的高能效电容开关转换方案

针对逐次逼近型模数转换器,提出了一种新型高能效的电容开关转换方案。在前3个比较周期内,该新型电容开关不消耗转换功耗。从第4个比较周期开始,采用了拆分电容技术、单边双电平转换技术,使得一侧的电容只在2个参考电压Vcm与地之间进行切换,进一步节省了功耗。仿真结果表明,与传统电容阵列相比,该新型电容开关的转换功耗降低了99.23%,总电容面积减小了75%。微分非线性为0.162 LSB,积分非线性为0.163 LSB。     

一种可校正的12位C2C电容阵列混合结构SAR ADC

提出了一种可校正的12位C2C电容阵列混合结构逐次逼近型模数转换器(SAR ADC),其数模转换器(DAC)由低6位分裂式C2C DAC阵列与高6位二进制DAC阵列构成。提出的混合结构DAC既解决了中高精度二进制SAR ADC中总电容过大的问题,又避免了分段式二进制DAC分数值桥接电容无法与单位电容形成匹配的问题。该结构能显著降低整个ADC的动态功耗。此外,将高位终端电容和低2~6位量化电容拆分成相等的两个电容,引入冗余量,使得该ADC的电容权重可以被校准,降低了电容失配以及寄生电容的影响。最后,为了避免电容上极板复位信号因电容阵列容值大而导致的延时偏大问题,采用高6位DAC采样的方式,并在高6位DAC中引入单位电容大小的终端电容,弥补了参考电压区间不完整的缺陷。仿真结果显示,在1.5 V电压下,该ADC总体功耗仅为111.84 μW,ENOB为12.49位,SFDR为91.46 dB,SNDR为76.97 dB。     

高精度SAR ADC电容阵列设计及校准算法

在高精度逐次逼近寄存器模数转换器(SAR ADC)中,电容阵列是SAR ADC的核心之一。电容阵列中的电容失配问题是导致转换精度降低的一个重要原因。为了尽可能改善这一问题,设计了一种6+6+6分段电容阵列,并且基于这种阵列设计了权重迭代算法的前台数字校准。该方法不需要额外的电容阵列,利用自身的电容阵列与比较器量化出电容失配,计算出每一位输出码的权重校准系数,用来对正常量化出的输出码进行编码,实现校准功能。仿真结果表明,引入电容失配的18 bit SAR ADC经过该算法校准后,信噪比(SNR)从77.6 dB提升到107.6 dB,无杂散动态范围(SFDR)从89.8 dB提升到125.6 dB,有效位数(ENOB)从12.54 bit提升到17.54 bit。在SMIC 0.18μm工艺下,该校准算法对高精度SAR ADC的动态性能具有较大提升。     

一种10位10 MS/s自补偿SAR A/D转换器

基于SMIC 0.18 μm CMOS工艺,设计了一种10位自补偿逐次逼近(SAR)A/D转换器芯片。采用5+5分段式结构,将电容阵列分成高5位和低5位;采用额外添加补偿电容的方法,对电容阵列进行补偿,以提高电容之间的匹配。采用线性开关,以提高采样速率,降低功耗。版图布局中,使用了一种匹配性能较好的电容阵列,以提高整体芯片的对称性,降低寄生参数的影响。在输入信号频率为0.956 2 MHz,时钟频率为125 MHz的条件下进行后仿真,该A/D转换器的信号噪声失真比(SNDR)为61.230 8 dB,无杂散动态范围(SFDR)达到75.220 4 dB,有效位数(ENOB)达到9.87位。     

一种新型的SAR ADC电容阵列混合转换方案

针对逐次逼近寄存器型模数转换器(SAR ADC),提出了一种高能效的新型混合转换方案,将单调转换方式、拆分电容转换技术与一种新型电容转换方式相融合。在前三次比较周期内,新型混合转换方案SAR ADC的电容阵列不需要电源补充能量;在剩余的比较周期内使用单调转换方式,使转换能耗进一步降低。同时,新型混合转换方案在采用更少电容的情况下,获得与传统结构相同的转换精度。模型仿真结果表明,采用新型混合转换方案后,SAR ADC电容阵列的转换能耗较传统结构减少了99%。     

一种串行逐次逼近10位 D/A转换器

首先对几种形式的D/A转换器进行了比较,设计了一种电容型D/A转换器。这些电容在逐次逼近结构中构成二进制权阵列。这种结构的D/A转换器动态范围大、建立时间短,精度易于保证;且它的温度系数、电压系数、功耗及面积均优于电阻型D/A转换器。在Cadence SpectreS环境下进行仿真验证,该转换器信噪比为49 dB,积分非线性为±0.5 LSB。     

一种基于损失电压分析的开关电容功率转换器静态模型

介绍了一种适用于多相交错开关电容功率转换器的静态模型。分析了电容与电容之间的电荷传递行为,将开关电容功率转换器中的电荷再分配损耗和开关导通损耗等价地描述为电荷传递子过程的电压损失。该模型可以简便、准确地描述任意开关频率下开关电容功率转换器的等效输出电阻。同时,运用了一种新的“比例电流近似”方法,建立了带电流负载时的电荷传递模型,用以描述和分析负载和输出去耦电容对电容功率转换器静态特性的影响。相比于传统模型,提出的模型在中等开关频率下能准确地描述开关电容功率转换器的静态特性,同时能准确地描述多相交错控制中开关电容功率转换器的输出电压纹波。     

13位高无杂散动态范围的SAR ADC

基于标准0.18μm CMOS工艺,设计了一款采样率为500 kSa/s的13位逐次逼近型模数转换器（SAR ADC）芯片。该转换器内集成了多路复用器、比较器、SAR逻辑电路和数模转换器（DAC）电容阵列等模块,实现了数字位的串行输出。使用7+6分段式电容阵列及下极板采样和电荷重分配原理,有效降低了ADC整体电容值及功耗。使用两级预放大的比较器和电荷存储技术降低了失调误差,比较器精度为0.3 m V。在2.5 V电源电压和500 kSa/s的采样率下,后仿真结果表明,ADC的无杂散动态范围为97.14 dB,信噪比为78.78 dB,有效位数为12.78 bit。     

一种低功耗16 bit逐次逼近型ADC的设计

设计了一种低功耗的16 bit 1 MSa/s逐次逼近型（SAR）模数转换器（ADC）。低功耗设计来源于电容阵列,其由3段子电容阵列构成,之间的桥接电容通过冗余电容和权重电容整数化。在电容阵列的切换过程中,通过将电容分裂来引入额外的参考电压。通过对量化噪声和热噪声的计算,可以精确地得出所需的电容数量为225个单位,相比于传统的电容阵列形式,可以节省99.93%的面积和99.5%的功耗。电路中使用一个2级预放大,并添加了具有自校零功能的动态锁存比较器,确保了高精度分辨率。在UMC 55 nm工艺下仿真,对512点的FFT仿真结果显示,ADC的整体信噪比（SNR）能够达到85.98 dB,有效位数（ENOB）能够达到13.884 1 bit,在电源电压为2.5 V的情况下,平均功耗为5.05 mW。     

一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

Ultra-low-power capacitor-splitting switching algorithm with minus energy for SAR ADCs

In this letter, an ultra-low-power capacitor-splitting switching algorithm for successive approximation register analog-to-digital converters is proposed. To achieve low power, the first three bit cycles consume no power from the reference by introducing minus energy during the third bit cycle and proper switching algorithm. To further reduce the switching energy, only single-side capacitors are switched from the forth bit cycle. Besides, to add one bit, the dummy capacitor is realized by four unit capacitors and switched to generate the least significant bit. Compared to the Sanyal and Sun switching technique, the proposed capacitor switching method achieves 94.19% energy saving and 47.66% capacitor area reduction.     

99.83% Switching energy reduction over conventional scheme for SAR ADC without reset energy

A high-efficient switching method for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. With the proposed variable resolution SAR ADC architecture, the average switching energy and area can be reduced by 99.60 and 73.54% respectively compared to the conventional scheme. Combined with C–2C capacitor array and unilateral monotonic scheme, the proposed two-step architecture achieves 99.83% less average switching energy and 76.37% less area reduction over the conventional approach. Furthermore, these two methods have no rest energy consumption.     

LSB split capacitor SAR ADC with 99.2% switching energy reduction

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.     

High energy-efficient partial floating capacitor array DAC scheme for SAR ADCs

A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. The proposed method can achieve high energy savings and high linearity due to the fact that the partial floating and split capacitor techniques are combined. This scheme has no reset energy consumption, and achieves purely 98.63% less switching energy and 75% reduction of the total capacitance over the conventional switching scheme. Moreover, the proposed scheme achieves Differential Nonlinearity and Integral Nonlinearity only 0.140LSB and 0.122LSB, respectively.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

无线携能网络中一种非线性能量收集与信息传输均衡策略

在无线携能(SWIPT)网络中,节点通常采用非线性能量收集。论文首先建立了非线性能量收集模型,提出了时隙切换与静态功率分割相结合的智能协同SWIPT传输方案(CoTP),推导了该传输方案的速率-能量(R-E)域,研究了接收端存在电路功耗情况下CoTP方案的速率-能量(R-E)均衡策略。同时,论文将所提的CoTP策略与动态功率分割(DPS)、开-关功率分割(OPS)、静态功率分割(SPS)与时隙切换策略(TS)的R-E域性能进行了比较,仿真分析了噪声以及接收端电路功耗对R-E域性能的影响。数值结果表明,与其他方案相比,若不考虑电路功耗情况,所提CoTP策略在每比特收集能量为0.6 mJ~2。4 mJ时具有较高的可达速率。若考虑电路功耗情况,所提CoTP策略在每比特收集能量为0 mJ~15 mJ时具有较高的可达速率,可以实现能量收集与信息传输的均衡。      

基于分段电容阵列的改进型逐次逼近型ADC

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed