掺硼和热处理对ZnO压敏电阻的电流稳定性的影响

本文研究了ZnO压敏电阻在交流和直流电压的长期作用下,漏电流的蠕变规律、Ⅴ-Ⅰ特性的变化以及热激活电流;在肖特基势垒热电子发射导电模型的基础上,分析了ZnO压敏电阻小电流性能的蜕变机制。从理论到实验研究了不同配方和工艺以提高ZnO压敏电阻的电流稳定性的方法。结果认为:适量的掺硼和适当的热处理工艺,都能改善ZnO压敏电阻的电流稳定性,而热处理方法更容易得到好的效果,同时也提出了上述方法对大电流性能可能带来的影响。     

直流作用下氧化锌压敏电阻极性效应分析

为了能够精确测量MOV(氧化锌压敏电阻)的老化程度,利用LPL-2型直流热稳定仪分别对MOV样品进行了正负直流老化实验,然后对老化MOV的静态参数进行了测量并描绘出了压敏电压的变化曲线以及小电流区的伏安特性曲线。结果表明:在单一直流作用下,MOV存在极性效应和伏安特性曲线蜕变,而且其伏安特性曲线蜕变在负向测量时较严重;在正负直流交替作用下,MOV的极性效应逐渐消失,但其伏安特性曲线仍存在蜕变。这为今后精确表征MOV的蜕变程度提供了新的思路。     

SnO2与ZnO压敏电阻特性比较分析

采用电子扫描显微镜对SnO2压敏电阻和ZnO压敏电阻内部结构进行了综合比较,并结合离子迁移理论,利用冲击发生器和热稳定仪器进行了大量实验,结果表明:SnO2压敏电阻较ZnO压敏电阻内部相态更简单、结构更均匀,在冲击老化和工频老化中表现更好;在大电流冲击时,SnO2压敏电阻的残压远远高于ZnO压敏电阻,这一缺陷限制了其在...     

低压TiO_2系压敏陶瓷的伏安特性实验分析

采用耗尽层近似理论,分析了低压TiO2系压敏陶瓷在直流偏压下的伏安特性,并对ZnO、TiO2和SrTiO3系三种压敏陶瓷的伏安特性进行了测试、分析和比较。结果表明,在晶界势垒不太高(一般为零点几电子伏)及晶界电场强度不太大(约106V/m量级)的情况下,TiO2系压敏陶瓷晶界的电子传输机制不同于ZnO系压敏陶瓷,而与SrTiO3系压敏陶瓷的导电机制相似,属于肖特基热电子发射机制。     

GaN基绿光LED芯片电流加速失效机理研究

采用电流加速的电应力老化方法研究GaN基绿光 LED芯片的失效机理。LED芯片在经过60 mA 电流老化424 h后,其发光效率总体趋势都是随老化时间增加而减小 ,但是小测量电流相比于大测量电 流的发光效率衰减程度更为明显。同时,在正向偏压下电流电压曲线基本没有变化,而反向 偏压下的反向 电流随老化时间的增加而快速增加。笔者认为在电应力老化作用下,随老化时间增加,有源 区的缺陷能级 增多,在正向偏压下,缺陷能级起到一个有效陷阱的作用,增加了载流子的寿命,降低了辐 射复合的几率, 使得发光效率降低,但是并没有减小正向偏压下的电流,而反向偏压时,缺陷能级起到了一 个漏电通道的作用,使得反向电流增大。     

BaBSi玻璃对ZnVSb基压敏电阻结构与性能的影响

通过传统工艺制备出Ba-B-Si玻璃相掺杂的Zn-V-Sb基压敏电阻材料,研究了其微观结构及性能。结果表明,Ba-B-Si玻璃相的掺杂能降低Zn-V-Sb基压敏电阻试样的烧结温度,玻璃相中B2O3的含量过多,会使ZnO压敏电阻材料的伏安(V-I)特性变差;而Ba2 含量的增加,使ZnO压敏电阻材料的非线性系数上升。     

ZnO压敏电阻的化学蜕变

ZnO压敏电阻在0.05mol/L NaOH的电解液中作直流电解处理后，出现化学蜕变，漏电流增加、非线性特性减弱，经热处理后其压敏特性又可恢复。它与通常的电学蜕变不同，经论证认为，这种蜕变是属于氢原子在瓷体晶粒边界附近中的还原作用所致。文中还讨论了其可能的蜕变机理。     

ZnO/p-Si异质结构的电学输运特性

采用等离子体浸没离子注入沉积方法,在p型Si衬底上制备了具有整流特性的、非故意掺杂的以及掺氮的ZnO/p-Si异质结.非故意掺杂的ZnO薄膜为n型(电子浓度为1019cm-3数量级),掺氮的ZnO薄膜为高阻(电阻率为105Ω·cm数量级).非故意掺杂的ZnO/p-Si异质结在正向偏压下,当偏压大于0.4V,电流遵循欧姆定律.然而对于掺氮的ZnO/p-Si样品,当偏压小于1.0V时,电流表现为欧姆特性,当偏压大于2.5V时,电流密度与电压的平方成正比的关系.分别用Anderson模型和空间电荷限制电流模型对非故意掺杂和掺氮的ZnO/p-Si异质结二极管的电流输运特性进行了解释.     

集成电路过压保护用ZnO压敏电阻的研制

为获得集成电路过电压保护用低压压敏电阻,以中压ZnO压敏电阻的配方为基础,通过研究与实验,确定了采用添加晶粒助长剂TiO2和籽晶、晶界稳定剂硼银玻璃和Ta2O5,低温烧结等途径,研制出了低压ZnO压敏电阻。测试结果表明,该ZnO压敏电阻的压敏电压为15~25V,漏电流小(<2μA),非线性特性好(α>29)。     

MgO掺杂对ZnO基线性电阻陶瓷性能的影响

以ZnO为基添加Al2O3和MgO制备了导电陶瓷;研究了MgO掺杂含量对ZnO陶瓷电阻率、电阻温度系数和相对密度的影响;测试分析了ZnO导电陶瓷在室温小电流时的伏安特性.结果表明,ZnO-Al2O3-MgO系陶瓷具有线性的伏-安(V-I)特性;添加MgO能增大电阻率且可改善电阻温度系数,当x(MgO) =5％时,小电流电阻率为178 Ω·cm,电阻温度系数为－1.5×10-3/℃;适量的MgO含量有利于烧结致密化.     

Influence of mechanical bending and temperature on the threshold voltage instability of a-Si:H thin-film transistors under electrical stress

This paper studies the electrical characteristics of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) under flat and bending situations after AC/DC stress at different temperatures. Stress temperature was varied from 77 K to 400 K, and threshold voltage shifts were extracted to analyze degradation mechanisms. It was found that high temperature and mechanical bending played important roles under AC stress, with an enhanced stress effect resulting in a more serious degradation. This study also discusses the dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress.     

Si/SiGe/SiHBT直流特性的可靠性

对单台面SiGeHBT在E-B结反偏应力下直流特性的可靠性进行了研究。研究结果表明,随应力时间的增加,开启电压增加,直流电流增益下降,特别是在低E-B正偏电压时下降明显;而交流电流增益退化缓慢。     

Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm²/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs

In this paper, the threshold voltage instability characteristics of HfO₂ high-k dielectric are discussed. The results from various stress bias conditions including DC and AC with variations of frequency, duty cycle, and polarity provide additional insights into the intrinsic behavior and the trapping dynamics of high-k materials. A reduced threshold voltage shift was observed at higher frequency and lower duty cycle under AC positive unipolar stress compared to DC stress. Similarly, the degradation of maximum transconductance was also reduced with AC stress. However, subthreshold swing changes were found to be negligible and fairly independent of stress frequencies and duty cycles under AC positive unipolar stress.When different polarity of stress, such as positive, negative, and bipolar stress was applied, it was observed that frequency and duty cycle dependencies were still valid in all three conditions. In contrast to positive stress, negative stress showed a decrease in the threshold voltage shift. Bipolar stress resulted in the highest threshold voltage instability, but the degradation in transconductance and subthreshold swing was actually smaller than those in negative unipolar stress. The bulk trap of HfO₂ dielectric, which is proportional to its physical thickness, is believed to be the primary factor for threshold voltage shift. AC unipolar operation would allow a higher 10-year lifetime operating voltage than the DC condition. In addition to experimental results, a plausible mechanism has been proposed.     

A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs

A comprehensive modeling framework involving mutually uncorrelated contribution from interface trap generation and hole trapping in pre-existing, process related gate insulator traps is used to study NBTI degradation in SiON and HKMG p-MOSFETs. The model can predict time evolution of degradation during DC and AC stress, time evolution of recovery after stress, impact of stress and recovery bias and temperature, and impact of several AC stress parameters such as pulse frequency, duty cycle, duration of last pulse cycle (half or full) and pulse low bias. The model can successfully explain experimental data measured using fast and ultra-fast methods in SiON and HKMG devices having different gate insulator processes. The trap generation and trapping sub components of the composite model have been verified by independent experiments. Data published by different groups are reconciled and explained. The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices.     

Electromigration under time-varying current stress

Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local V_CC and V_SS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.     

氧化锌压敏电阻器的失效模式

在生产和应用中,氧化锌压敏电阻器经常出现的几种失效模式为:与电极层相关的失效,平均功率过应力失效与受潮失效。通过对这些失效现象的进一步分析和研究,掌握了产生这些现象的机理和规律,并可以增加压敏电阻的电极层厚度,降低其电阻;对于34mm×34mm的SPD用电阻片,可用In为15kA作为标称放电电流;受潮失效后的压敏电阻,不会导致电路故障,通过侧面绝缘处理,可防止受潮失效。     

交流信号对亚微米CMOS集成电路可靠性的影响

介绍了交流信号对亚微米CMOS集成电路可靠性的影响,重点分析了亚微米CMOS集成电路中交流应力下的热载流子效应、电迁移、栅氧化层介质击穿效应。通过与直流应力下器件可靠性的对比,分析交流信号与直流信号对亚微米CMOS集成电路可靠性影响的差异。