An amorphous SiC:H emitter heterojunction bipolar transistor

After confirming the successful application of the amorphous SiC:H(a-SiC:H)/crystalline Si(c-Si) heterostructure in a solar cell and considering its prospective application in Bi-CMOS devices, an attempt has been made to apply the same in the fabrication of a heterojunction bipolar transistor. A p-n-p heterojunction bipolar transistor with a wide band-gap boron-doped amorphous SiC:H emitter and crystalline Si (base, collector) has been realized and is reported here for the first time. Good device performance has been observed at the a-SiC:H deposition temperature of 450°C. Preliminary results gave a current gain,h_{FE(max)}) of 50 at a current density of approximately 2.4 A/cm²(base dose 2 × 10¹²/cm², width ≃ 0.4 µm). Temperature dependence of the transistorh_{FE}-I_{C}characteristics was also studied.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Electroluminescence characteristics and current-conductionmechanism of a-SiC:H p-i-n thin-film light-emitting diodes with barrierlayer inserted at p-i interface

In order to improve the electroluminescence (EL) characteristics of the hydrogenated amorphous silicon carbide (a-SiC:H) p-i-n thin-film light-emitting diode (TFLED), a barrier layer (BL) was inserted at its p-i interface to enhance the hole injection efficiency under forward-bias operation. The a-SiC:H TFLED's with various optical gaps of BL had been fabricated and characterized. In addition, a composition-graded n⁺-layer was used to reduce its series and contact resistances to the Al electrode and hence the EL threshold voltage (V_th) of an a-SiC:H BL TFLED. The highest obtainable brightness of an a-SiC:H BL TFLED was 342 cd/m² at an injection current density of 600 mA/cm² and the lowest EL V _th achievable was 6.0 V. The current-conduction mechanism of an a-SiC:H BL TFLED had also been investigated. Within the lower applied-bias region, it showed an ohmic current, while within the higher applied-bias region, a space-charge-limited current (SCLC) was observed     

Low-temperature growth of polycrystalline SiC by catalytic CVD from monomethylsilane

Microcrystalline silicon carbide (μc-SiC) has several applications, such as solar cells, light-emitting diodes and as optical coating for solar cells. Hydrogenated amorphous silicon carbide (a-SiC:H) grows by plasma enhanced CVD, even under hydrogen diluted conditions. High concentration of atomic hydrogen from catalytic CVD could promote lower temperature growth of μc-SiC under the same conditions as a-SiC:H without plasma. In the present study, μc-SiC films have been successfully grown by catalytic CVD (hot-filament catalysis) from monomethylsilane and hydrogen on (1 0 0) silicon substrates maintained at 300 °C. The optimal chamber pressure is 1.0 Torr and the optimal concentration of monomethylsilane in the hydrogen carrier gas is 1%. FTIR spectra of films obtained under these conditions show strong Si-C peaks.     

异质结硅太阳能电池a—Si：H薄膜的研究

通过应用Scharfetter-Gummel数值求解Poisson方程，对热平衡态P^ （a-Si:H)/n(c-Si)异质结太阳能电池进行计算机数值模拟分析。结果指出，采用更薄P^ (a-Si：H）薄膜设计能有效增强光生载流子的传输与收集，从而提高a-Si/c-Si异质结太阳能电池的性能。同时，还讨论了P^ (a-Si:h)薄膜中P型掺杂浓度对光生载流了传输与收集的影响。高强茺光照射下模拟，计算表明，a-Si/c-Si异质结结构太阳能电池具有较高光稳定性。     

Optoelectronic characteristics of a-SiC:H-based P-I-N thin-filmlight-emitting diodes with low-resistance and high-reflectance N+-a-SiCGe:H layer

The graded-gap a-SiC:H-based p-i-n thin-film light-emitting diodes (TFLEDs) with an additional low-resistance and high-reflectance n⁺ -a-SiCGe:H layer were proposed and fabricated on indium-tin-oxide (ITO)-coated glass substrate in this paper. For a finished TFLED, a brightness of 720 cd/m² could be obtained at an injection current density of 600 mA/cm², and its EL (electroluminescence) threshold voltage was lowered to 8.6 V. In addition, the effects of reflectance and resistance of a-SiCGe:H film on the performance of TFLED were discussed. The optimum rapid thermal annealing (RTA) conditions for fabrication of TFLED after metallization were also studied and employed to improve the optoelectronic characteristics of TFLED     

Optimization of Al/a-SiC:H optical sensor device by means of thermal annealing

The optimization of optoelectronic properties of Al/a-SiC:H Schottky diodes grown as Al/a-SiC:H/c-Si(n) structures is studied by means of thermal annealing of a-SiC:H thin films. According to the spectral response of the Schottky diodes the measured quantum efficiency, η_measured, increases with increasing annealing temperature (400–600 °C), whereas η_measured decreases for T_a>600 °C. For T_a=600 °C, optimum material quality of a-SiC:H films is achieved and the spectral response of the Al/a-SiC:H/c-S(n) structures present very high and almost constant values (η_measured80%) for the whole range of wavelengths from 500 up to 850 nm. These results show that our Al/a-SiC:H/c-S(n) structures can be very attractive as optical sensors. Diffusion length calculations as well as the mobility by lifetime product (μτ)_p of the minority carriers (holes) of a-SiC:H films present a dependence on T_a similar to that of the measured quantum efficiency. Finally, the quantum efficiency of films processed with T_a=675 °C is found to increase when the Al/a-SiC:H/c-S(n) structures are exposed to hydrogen, a result that could be promising for the construction of a hydrogen detection sensor.     

Simulation analysis of the effects of a back surface field on a p-a-Si:H/n-c-Si/n+-a-Si:H heterojunction solar cell

In order to investigate the effects of a back surface field（BSF） on the performance of a p-doped amorphous silicon（p-a-Si：H）/n-doped crystalline silicon（n-c-Si） solar cell,a heterojunction solar cell with a p-a-Si：H/n-c-Si/n^＋-a-Si：H structure was designed.An n^＋-a-Si：H film was deposited on the back of an n-c-Si wafer as the BSF.The photovoltaic performance of p-a-Si：H/n-c-Si/n^＋-a-Si：H solar cells were simulated.It was shown that the BSF of the p-a-Si：H/n-c-Si/n^＋-a-Si：H solar cells could effectively inhibit the decrease of the cell performance caused by interface states.     

Simulation analysis of the effects of a back surface field on a p-a-Si:H/n-c-Si/n+-a-Si:H heterojunction solar cell

In order to investigate the effects of a back surface field (BSF) on the performance of a p-doped amorphous silicon (p-a-Si:H)/n-doped crystalline silicon (n-c-Si) solar cell, a heterojunction solar cell with a p-a-Si:H/nc-Si/n+-a-Si:H structure was designed. An n+-a-Si:H film was deposited on the back of an n-c-Si wafer as the BSF.The photovoltaic performance of p-a-Si:H/n-c-Si/n+-a-Si:H solar cells were simulated. It was shown that the BSF of the p-a-Si:H/n-c-Si/n+-a-Si:H solar cells could effectively inhibit the decrease of the cell performance caused by interface states.     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

Large-Grain Polycrystalline Silicon Solar Cell on Epitaxial Thickening of AIC Seed Layer by Hot Wire CVD

Large-grain polycrystalline silicon (poly-Si) films were prepared on foreign substrates by the epitaxial thickening of seed layers. The seed layers were formed by aluminum-induced crystallization (AIC). Large-grain n-i-p poly-Si solar cells were deposited on epitaxial seeds by hot-wire chemical vapor deposition (HWCVD). Highly (93%) crystalline fractions with a lateral grain size of 5 ?m and an intrinsic layer were grown without incubation. These techniques were employed to prepare large-grain poly-Si thin-film solar cells. An ITO/n-i-p (HWCVD)/p+ (AIC)/Ti/glass-structured poly-Si thin-film solar cell with an initial efficiency of 5.6% was obtained.     

A study of the i/p interface for flexible n–i–p a-Si:H thin film solar cells

In this paper, the influence of i/p interface buffer layer on the performance of flexible n–i–p a-Si:H thin film solar cells is studied. The results show that the dopant distribution in the buffer layer has large effect on the property of solar cells. A larger open circuit voltage and fill factor can be obtained when methane is introduced into the chamber prior to diborane during the deposition of buffer layer. The AMPS simulation indicates that it is beneficial to improve the built-in electric field in the i layer when the carbon is doped prior to boron, thus the carrier transport properties are improved. By further optimizing the deposition parameter, an initial conversion efficiency of 5.668% is achieved for the a-Si:H thin film solar cells on the PI substrates at 150 °C.     

An amorphous SiC/Si two-color detector

A glass/ITO/(n⁺-i) a-SiC:H/(p⁺-i-n⁺) a-Si:H/A1 photodetector with a voltage-selectable spectral response was fabricated successfully. It consists of two back-to-back p-i-n junctions, including an a-SiC:H/a-Si:H heterojunction and a-Si:H homojunction. As the bias at the ITO side changes from 2 to -2 V, the responsivity to light with a wavelength of 6000 Å increases 18 times, whereas for light of 4500 Å, it decreases three times. The detectivity ratio at these two wavelengths then changes from 0.16 to 4 which provides a good distinction between two colors, i.e., orange and blue.     

New self-aligned T-gate InGaP/GaAs field-effect transistors grownby LP-MOCVD

This paper reports on self-aligned T-gate InGaP/GaAs FETs using n ⁺/N⁺/δ(P⁺)/n structures. N⁺ -InGaP/δ(P⁺)-InGaP/n-GaAs forms a planar-doped barrier. The inherent ohmic gate of camel-gate FETs together with a highly selective etch between an InGaP and a GaAs layers offers a self-aligned T-shape gate with a reduced effective length. A fabricated device with a reduced gate dimension of 1.5×100 (0.6×100) μm² obtained from 2×100 (1×100) μm² gate metal exhibits an extrinsic transconductance, unity-current gain frequency, and unity-power gain frequency of 78 (80) mS/mm, 9 (19.5), and 28 (30) GHz, respectively     

Low-resistivity poly-metal gate electrode durable forhigh-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN_x(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800°C. The sheet resistivity of the W(100 nm)/WN_x (5 nm)/poly-Si(100 nm) structure is as low as 1.5 Ω∥□ and independent of line-width from 0.52 μm to 0.12 μm. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Excellent low-pressure-oxidized Si3N4 filmson roughened poly-Si for high-density DRAMs

High-reliability and good-performance stacked storage capacitors with high capacitance value of 17.8 fF/μm² has been realized using low-pressure-oxidized thin nitride films deposited on roughened poly-Si electrodes. These novel electrodes are fabricated by H ₃PO₄-etching and are RCA-cleaned. The leakage current density at +2.5 and -2.5 V are 0.07×10^-9 and -2.4×10^-8 A/cm², respectively, fulfilling the requirements of 256 Mb DRAM's. Weibull plots of time-dependent-dielectric-breakdown (TDDB) characteristics under constant current stress and constant voltage stress also show tight distribution and good electrical properties. Hence, this easy and simple technique is promising for future high-density DRAM's applications     

Influence of absorber doping in a-SiC：H/a-Si：H/a-SiGe：H solar cells

This work deals with the design evaluation and influence of absorber doping for a-Si:H/a-SiC:H/a-SiGe:H based thin-film solar cells using a two-dimensional computer aided design (TCAD) tool. Various physical parameters of the layered structure, such as doping and thickness of the absorber layer, have been studied. For reliable device simulation with realistic predictability, the device performance is evaluated by implementing necessary models (e.g., surface recombinations, thermionic field emission tunneling model for carrier transport at the heterojunction, Schokley-Read Hall recombination model, Auger recombination model, bandgap narrowing effects, doping and temperature dependent mobility model and using Fermi-Dirac statistics). A single absorber with a graded design gives an efficiency of 10.1% for 800 nm thick multiband absorption. Similarly, a tandem design shows an efficiency of 10.4% with a total absorber of thickness of 800 nm at a bandgap of 1.75 eV and 1.0 eV for the top a-Si and bottom a-SiGe component cells. A moderate n-doping in the absorber helps to improve the efficiency while p doping in the absorber degrades efficiency due to a decrease in the V_OC (and fill factor) of the device.     

Influence of buffer layer thickness on DC performance ofGaAs/AlGaAs heterojunction bipolar transistors grown on siliconsubstrates

The DC performance of GaAs/AlAs heterojunction bipolar transistors (HBTs) grown on silicon substrates with buffer layers ranging from 0 to 5 μm was investigated. Current gain, collector-emitter breakdown voltage, emitter-base and collector-base diode ideality factors, and breakdown voltages were measured as the buffer layer thickness was varied between 0 and 5 μm. The current gain steadily increases with increasing buffer layer thickness until the layer reaches 3 μm. However, the other DC parameters are relatively insensitive to the buffer layer thickness. A small-signal current gain of 60 is typically achieved for devices with 6×6-μm² emitters at a density of 6×10⁴ A/cm² when the buffer layer is ⩾3 μm     

Impact of Ge implantation on the electrical characteristics of TiSi2 p+/n shallow junctions with an a-Si (or apoly-Si) buffer layer

A new technology for forming a titanium-silicide shallow junction by combining germanium implantation with an amorphous-silicon (or a poly-silicon) buffer layer has been proposed for MOSFETs. The use of a buffer layer between Ti and Si can avoid the consumption of bulk-silicon and the recession of TiSi₂ film into the source/drain junctions during the silicidation process. In this study, the important role of germanium-implantation on the formation of TiSi₂ contacted p⁺/n junctions was examined. After subsequent implantation of Ge⁺ and B⁺ into the TiSi₂ film, samples were annealed at different temperatures to form p ⁺/n junctions and C54-TiSi₂. Since the penetration of titanium atoms was suppressed due to the germanium-implantation, the periphery leakage and the generation leakage were improved and TiSi₂/Si interfaces were even smooth. Therefore, p⁺/n junctions with a very low leakage current (0.192 nA/cm ² at -5 V) and an excellent forward ideality factor (n≈1.002) can be obtained. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth is 400