Modeling and sensitivity analysis of circuit parameters for flip-chip interconnects using neural networks

This paper presents a neural network-based technique for modeling and analyzing the electrical performance of flip-chip transitions. A lumped element model using a simple pi equivalent circuit is used to characterize the electrical properties of the flip-chip bond. Statistical experimental design is used to extract the electrical parameters for flip-chip characterization from measurements and full-wave simulations up to 35 GHz. The extracted data is used to train back-propagation neural networks to obtain an accurate model of the pi equivalent circuit components and s-parameters as a function of layout parameters. The prediction error of the models is less than 5%. The models are used to obtain response surfaces for the entire range of variation of layout parameters. The neural network models are subsequently used to perform sensitivity analysis. All electrical parameters are shown to be sensitive to conductor overlap. The inductance and capacitance of the pi equivalent circuit are sensitive to the bump height. However, the return loss (S₁₁) is insensitive to the change in bump height. The coplanar waveguide width has a significant impact on the s-parameters, as it affects the matching of flip-chip transitions     

Hybrid integration of surface-emitting microlaser chip and planaroptics substrate for interconnection applications

The bonding of a monolithic array of surface-emitting microlasers onto a glass substrate that contains a matching array of microlenses and mirrors is reported. The bonding was achieved by flip-chip solder bump bonding using indium as the solder material. The alignment precision is within ±2 μm. The optical substrate provides a simple interconnection scheme that routes the light from each laser to well defined output positions     

The flip-chip bump interconnection for millimeter-wave GaAs MMIC

The flip-chip bump interconnection structure has become popular for microwave and millimeter-wave package applications. This structure is expected to provide higher performance and a low cost packaging method. This paper presents the results of an evaluation of flip-chip assembled radio frequency (RF) devices. A coplaner transmission line type GaAs monolithic microwave integrated circuit (MMIC) was mounted on an aluminum oxide (Al₂O₃) substrate using the flip-chip thermal compression method. The electrical performance (S-parameter and noise figure) was measured and the reliability of the interconnection was tested. The changing rate of the characteristic impedance (Zo) of transmission line on bare-chip caused by bare-chip surface proximity to a substrate was simulated by finite element method (FEM) analysis. Flip-chip bonding conditions were fixed to keep the gap that less than 1% of Zo changing rate and sufficient bonding strength for reliability of interconnection. The DC characteristics of a 30 GHz, 60 GHz and 77 GHz band low noise amplifier (LNA) were the same before and after mounting, and the RF performance of the assembled MMIC was the same as the bare-chip without packaging. However, the influence of underfilling was observed. When epoxy resin was injected into the gap between the bare-chip and the substrate, the frequency band of the MMIC shifted to the low side. The reliability of the bump interconnection was excellent. The interconnection resistance did not change in a temperature cycle (-55°C to +125°C until 1500 cycle) test     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology     

Electroless remetallization of aluminum bond pads on CMOS driverchip for flip-chip attachment to vertical cavity surface emitting lasers(VCSEL's)

A method for remetallizing the bond pads of electronic chips, which are initially metallized with aluminum or aluminum alloy is presented. Application of electroless plating process for the remetallization of aluminum to a solderable gold surface can reduce the cost and complication of the widely accepted flip-chip interconnection technology. We have developed a step by step nickel/gold wafer bumping technique (remetallized bump height is 5.0 μm) for the appropriate solder (15.0 μm of In:Pb). Variation of roughness of the remetallized surface has been studied carefully. We have completed prototype research studies on test devices and successfully packaged the flip-chip bonded hybrid pair of a CMOS driver chip and a dummy structure of vertical cavity surface emitting laser (VCSEL) array. Cross section of the flip-chip solder joint is studied. Also, adhesion strength of the metal deposit is investigated     

Flip-chip planar GaInAs/InP p-i-n photodiodes-fabrication andcharacteristics

New flip-chip planar GaInAs/InP p-i-n photodiodes have been fabricated as an array. We describe the structure of the photodiode, the design of a microlens, the fabrication processes, characteristics, and the optical fiber-coupled modules. This photodiode satisfied the requirements for a small junction capacitance and low dark current, good optical fiber coupling, and easy fabrication. We obtained a low dark current with good reproducibility by using two layer polyimide and SiN passivation films. A microlens with a 50 μm φ to 120 μm φ aperture could easily be fabricated with an InP-substrate. By electroplating, flip-chip metal bumps were directly formed on the active region of the photodiode for the first time     

RF packaging and passives: design, fabrication, measurement, and validation of package embedded inductors

Design, modeling, and characterization of inductors embedded in a package substrate promising higher quality factor (Q) and lower cost than on-chip inductors is described. In addition to the problem of large conductor losses, on-die inductors with or without magnetic materials consume considerable die area and require the removal of the first-level interconnect bumps beneath them to maintain a reasonably high Q value. Moving inductors to the package eliminates the need for bump array depopulation and, thus, mitigates the potential reliability problems caused by voids in the epoxy underfill between the die and the substrate. Competency developed to design, fabricate, and characterize inductors based on standard organic flip-chip packaging technology is described. Physical design details along with measurement procedures and results are discussed. In addition, modeling techniques for achieving good correlation to measured data are included.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Novel micro-bump fabrication for flip-chip bonding

This paper describes a new bump-fabrication technique for flip-chip connection between a chip and substrate. We propose a novel idea of forming solder microbumps on the substrate and directly bonding bare chips to the substrate. We successfully achieved the new flip-chip connection by using a 0.05Au-0.95Sn solder bump and a hydrogen-plasma reflow technique. Because the method eliminates the need for any process on the chip wafer, it will be very useful in fabricating flip-chip connections for low-cost packaging.     

Improved Thermal Performance of AlGaN/GaN HEMTs by an Optimized Flip-Chip Design

AlGaN/GaN high electron mobility transistors (HEMT) on sapphire substrates have been studied for their potential application in RF power applications; however, the low thermal conductivity of the sapphire substrate is a major drawback. Aiming at RF system-in-a-package, the authors propose a flip-chip-integration approach, where the generated heat is dissipated to an AlN carrier substrate. Different flip-chip-bump designs are compared, using thermal simulations, electrical measurements, micro-Raman spectroscopy, and infrared thermography. The authors show that a novel bump design, where bumps are placed directly onto both source and drain ohmic contacts, improves the thermal performance of the HEMT     

Preventing a "noisequake" [substrate noise analysis]

Substrate noise analysis can identify potential problems in mixed-signal and RF designs. In this paper substrate noise analysis was described and the methodology used in Cadence's SeismIC tool, a 3D solver, was discussed in detail. Several results were presented to demonstrate the accuracy of substrate extraction. Good correlation was shown between SeismIC and the 2D solver, Medici, for two structures in a TSMC 0.18 μm process. The overall average error in magnitude of the impedance for the two structures was 1.4 dB. Excellent correlation was demonstrated between SeismIC and measured impedances. The average magnitude of error between simulations and measurements was 6.4%. Another example of comparison of SeismIC with silicon was shown for a mixer fabricated in 0.6 μm technology. Measured gain showed excellent correlation to that simulated using a circuit simulator, with a substrate annotated netlist computed using SeismIC extraction. The SeismIC simulation flow was demonstrated for an Ethernet transceiver chip containing one million devices. This example shows the utility of using substrate analysis in the debug phase of a design, the value of identifying the worst noise contributors for a given design, and using analysis in the design phase to optimize the noise immunity of a design     

Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

Wideband scalable electrical model for microwave/millimeter waveflip chip interconnects

We present a method for developing fully scalable lumped element models for flip chip interconnects. Measurements of test structures and full wave simulations are used to generate circuit models for various single bump configurations. Furthermore, regression models are developed for scaling the values of the elements with the physical attributes of the circuit. First, the method is validated using only two factors, then the model is extended to more inputs related to the bump geometry and placement. The values of L and C in a simple π model have been scaled with the conductor overlap, the distance from the ground bump to the edge of the ground plane, the width of the CPW launch, the bump height and diameter. Explicit formulas are obtained for L and C as a function of those variables. It has been found that the value of the inductance varies with the conductor overlap, bump height and diameter, while the capacitance is mostly affected by conductor overlap. This paper presents the first fully scalable model for microwave flip chip technology     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

Controllability of novel Sn/sub 0.95/Au/sub 0.05/ microbumps using interlaminated tin and gold layers for flip-chip interconnection

A flip-chip interconnection technology using novel lead-free solder microbumps with a balling temperature as low as 220 /spl deg/C is presented. Controllability of newly developed Sn/sub 0.95/Au/sub 0.05/ microbumps has been examined experimentally. By varying the bump volume and the diameter of the wettable bump electrodes, Sn/sub 0.95/Au/sub 0.05/ microbumps with heights from 11 /spl mu/m to 37 /spl mu/m were successfully fabricated with a standard deviation of 1.5 /spl mu/m. The deviation of on-chip CPW impedance from 50 /spl Omega/ was lower than 10% for nonmetallization motherboard. The smaller bumps exhibited a better performance since the degradation of reflection properties is ascribed to the bump capacitance, which was estimated 10-20 fF. Because of high process yield and good performance, the flip-chip bonding using Sn/sub 0.95/Au/sub 0.05/ microbumps of the order of 20 /spl mu/m in height may be advantageous for W-band interconnection of InP- or GaAs-based devices.     

Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

PtSi 256×256 IRCCD微型化封装技术研究

采用倒装焊接技术,实现了PtSi 256×256 IRCCD微型化封装。对金属凸点、引线衬底的制备以及倒装焊接技术进行了研究。     

Very large arrays of flip-chip bonded 1.55 μm photodetectors

We present very large arrays of InGaAs-InP p-i-n photodetectors flip-chip bonded to Si. The photodiodes are designed for operation at zero bias, e.g., for spectroscopic applications. Our design maintains depletion at zero bias resulting in ~99% photocurrent collection efficiency. The series resistance of our photodiodes is <1 Ω for a 40×40 μm device, including the flip-chip bond, resulting in high tolerance to shunt leakage. We produce arrays of photodiodes as large as 120 and measure leakage currents. We analyze zero-bias photocurrent generation in the presence of leakage and determine that with this technology arrays as large as 128 can be produced with high yield. The concept of redundancy in zero-bias photodiode arrays is presented and explored. Under the assumption that photodiode leakage is produced by microscopic point defects, a substantial increase in uniformity can be achieved in photodetector arrays by employing redundancy