合成瞬时带宽超宽的新型YIG调谐带通滤波器

基于功率分配-滤波-通带合成的原理,设计了一种合成瞬时带宽超宽的新型YIG调谐带通滤波器,其合成瞬时带宽是两只YIG调谐带通滤波器瞬时带宽之和,损耗等于分支路上的功分器、YIG滤波器、合路器的损耗之和。用两只工作频率6～18GHz、3dB带宽等于400MHz的YIG调谐带通滤波器合成为瞬时带宽大于800MHz超宽带YIG调谐滤波器,设计结果证明了这种方法的可行性和理论的正确性。     

YIG调谐滤波器锁相自跟踪技术方案设计与实现

介绍了一种利用YIG调谐滤波器锁相自跟踪技术解决因磁滞、调谐非线性、温度漂移等影响其频率准确度的方法。着重叙述了锁相自跟踪的工作原理、设计方案及预选/跟踪滤波器、锁相电路等设计技术。超外差接收前端的中频差频与YIG调谐滤波器的自跟踪技术结合可在增强射频信号预选特性的同时有效提升工作频率的准确度,此外,YIG调谐滤波器的良好线性调谐特性可使得锁相自跟踪环路在整个工作频带内具有良好的一致性。器件实测结果表明,在2~18 GHz频率范围内,频率准确度优于±1.5 MHz,方案的合理性和技术的先进性对YIG调谐滤波器在高性能电子设备中的应用有较大的参考意义和实用价值。     

1～1.5GHz宽带梳状线电调滤波器的研究与设计

介绍了一种宽带梳状线电调滤波器的设计方法。推导出微带线自电容和互电容与耦合系数的表达式,通过研究耦合系数对调谐带宽的影响,提出了实现宽带调谐的优化方法,给出滤波器的微带线尺寸设计公式。设计了调谐范围为1～1.5GHz、插入损耗小于7.5dB、1dB相对带宽为4%±1%的连续电调梳状线滤波器。     

同步调谐可变带通滤波器的设计

中心频率固定而带宽变化的可变带通滤波器广泛应用在许多电子测量仪器中,本文首先介绍了可变带通滤波器的实现背景,并着重介绍了可利用同步调谐滤波器来实现这种滤波器的理论依据和实际电路.通过电路分析和数学推导可以证明,电路中采用幅度补偿是可行的,并具有优势.     

文摘

电力滤波器调谐特性分析仪的研究[中]／王喜银,孙伟红,肖颍涛,等／／电气技术．2009（6）．-31～33针对电网交流滤波器特性测试的需要,设计一种便携式的单相电力滤波器调谐特性分析仪,对其工作原理进行理论分析和仿真研究,并设计相应的单相逆变器及高速数据采集装置,实现快速、便携的对现场多组电力滤波器的调谐特性进行测试。图6表1参6     

电力滤波器调谐特性分析仪的研究

针对电网交流滤波器特性测试的需要,设计一种便携式的单相电力滤波器调谐特性分析仪,对其工作原理进行理论分析和仿真研究,并设计相应的单相逆变器及高速数据采集装置,实现快速、便捷的对现场多组电力滤波器的调谐特性进行测试。     

文摘

电力滤波器调谐特性分析仪的研究[中]／王喜银,孙伟红,肖颍涛,等／／电气技术．2009（6）．-31～33针对电网交流滤波器特性测试的需要,设计一种便携式的单相电力滤波器调谐特性分析仪,对其工作原理进行理论分析和仿真研究,并设计相应的单相逆变器及高速数据采集装置,实现快速、便携的对现场多组电力滤波器的调谐特性进行测试。图6表1参6     

基于F-P可调谐滤波器的光纤光栅解调系统设计

针对某结构应力监测系统,提出应用光纤光栅传感原理来测量结构应力,设计了基于光纤标准具的F-P可调谐滤波器光纤光栅解调系统。利用标准具的稳定性来对F-P滤波器进行标定,消除环境温度对F-P滤波器的干扰。利用DDS原理设计了F-P滤波器的驱动源,产生的三角波分辨率可以小于0.42mV,确保解调系统最终的分辨率达到1pm。设计了光电转换电路,实现了微弱光信号的转换和放大,最后转换成易于采集与显示的电压信号。最终,利用本次设计的解调系统可以实现±3000με的应变测量,测量精度可达到2.59%。     

信号分析仪器中YIG滤波器快速调谐技术研究

在信号分析仪器中,YIG滤波器应用于射频通路前端以有效滤除镜频信号。由于它是一种由磁性材料研制而成的可调谐带通滤波器,涡流、电感、磁滞特性决定了其快速调谐过程中频率响应总是滞后于调谐电流,严重影响了信号分析仪扫描速度的提升。根据YIG滤波器特性及提供激励源驱动电路特点,提出了驱动补偿概念,用驱动补偿抵消磁滞效应带来的滞后。重点介绍了点补偿、扫补偿等驱动补偿的实现方法。通过在某型号信号分析仪上验证,结果表明采用该方案可有效地实现YIG滤波器的快速调谐,可将信号分析仪的扫描速度提高到200MHz/ms,有效改善了信号分析仪的测量效率。     

基于中心对称结构的带宽可重构滤波器设计

为适应需求日益复杂的无线通信环境，充分利用紧缺的频谱资源，设计实现了基于中心对称结构及变容二极管的电可调微带带通滤波器。通过电磁仿真软件HFSS进行仿真实验，在加载枝节的开口环谐振器结构上，引入叉指结构和马刺线型耦合馈线完成滤波器的原型设计。在原有的基础上加入可调节电容值的变容二极管，调节低频传输零点，实现通带带宽可重构，从而达到灵活控制滤波性能的目的。实际测试表明该滤波器的初始相对带宽为5.1%,初始绝对带宽为170 MHz,变容二极管调节绝对带宽在140～200 MHz范围内，即82.4%～117.6%,中心频率在2.70～2.76 GHz,传输零点调谐范围在2.57～2.63 GHz,通带内插入损耗在0.9～1.5 dB,回波损耗在10～35 dB,测试结果与仿真基本相符，在S波段的带宽精密控制方向具有一定应用前景。     

A dual-mode tunable bandpass filter for GSM,UMTS, WiFi,and WiMAX standards applications

This paper presents a dual-mode tunable bandpass filter (BPF) for global system for mobile communication, universal mobile telecommunications system, wireless fidelity, and worldwide interoperability for microwave access standard applications. The proposed filter consists of a stepped-impedance resonator, single resonator, and coupled line, which are loaded with varactors. The center frequency and bandwidth of the proposed filter can be tuned with tuning varactors. Furthermore, the measurement results show that the BPF can be tuned over the frequency range of 1.8 to 2.5 GHz. Moreover, the bandwidth can be changed at each certain frequency. Furthermore, using PIN diodes, a bandstop filter is added to the tunable BPF to reduce the out-of-band frequencies around the desired frequencies. The values of LC equivalent circuits are calculated, and the results are compared with those obtained from the layout of the proposed structure. Finally, the measurement results justify the simulation results.     

LC滤波器设计方法介绍及其仿真特性比较

对低通滤波器（LPF）的设计方法进行介绍,包括定K型及m推演形LPF,并利用滤波器设计软件Ansoft Designer对所设计的滤波器进行特性仿真和比较。最后简单介绍了一下LC高通（HPF）和带通（BPF）滤波器的设计方法。本文的介绍对滤波器设计理论基础有了更透彻了解,也为更好设计滤波器软件提供了理论指导。     

基于等效电路模型的细胞内外膜跨膜电位频率响应

提出一种适用于高频范围分析的细胞等效电路模型,给出了细胞内外膜跨膜电位的计算公式,对其频率响应进行仿真分析表明,细胞外膜跨膜电位频率响应可视为一阶低通滤波器,而内膜跨膜电位频率响应可视为一阶带通滤波器.应用指数衰减陡脉冲对人卵巢腺癌SKOV3细胞进行处理,实验结果和频谱分析表明,指数衰减陡脉冲的下降沿和上升沿分别包含了大量的低频和高频分量,分别作用于肿瘤细胞的外膜和内膜,从而对整个肿瘤细胞产生普遍的杀伤作用.     

A closed loop inductorless equalizer with a modified analysis of power comparator behaviour

Inductorless circuits are gaining advantage in radio frequency (RF) and high-speed serial link circuits due to the reduced silicon area. This paper presents an inductorless adaptive analog equalizer using an adaptive hybrid filter comprising integrated low pass and high pass filter. The equalizer, designed and fabricated in 180-nm CMOS technology, is able to adjust the high-frequency boost (HFB) and cutoff frequency of the internal filters depending on the data rate and the channel loss. The presented equalizer operates at data rates more than 4 Gbps in post-layout simulation without electrostatic discharge (ESD) and package parasitics. For the test purposes, the equalizer has been packaged in QFN 64 pin package and hence the measurement results are up to 3.125 Gbps. The measurement results show that the equalizer is able to adapt the HFB for the channel losses as high as 5 dB. Average dissipated power of the equalizer at 3.125 Gbps is 18 mW with 1.8-V supply. After reading this chapter you should be able to understand the merits of the proposed hybrid filter compared with the conventional RC filters in the adaptive equalizer using spectrum balancing technique; theoretical analysis and the impact of short channel effects on the performance of the power comparator; and test results of the adaptive equalizer using the proposed hybrid filter in the spectrum balancing technique.     

LFMCW雷达差频信号滤波电路设计

理想情况下LFMCW雷达差频信号在规则区内是标准正弦信号,但大量实测信号表明,差频信号中含有成分复杂的噪声信号,严重影响了雷达的测距精度.采用模拟滤波器,是滤除这些噪声信号最直接的办法.针对LFMCW雷达差频信号信号频带与噪声频带相近的特点,介绍了一种计算简单的模拟椭圆滤波器设计方法,分别设计了椭圆函数低通、高通滤波器,然后通过级联的方式构成带通滤波器.实测实验表明,该方法设计的带通滤波器可以有效地降低噪声干扰,提高LFMCW雷达差频信号质量.     

A systematic class AB state space synthesis method based on MOSFET square law and translinear square‐root cells

A new state space Class AB synthesis method for the design of square‐root domain filter based on the MOSFET square law is proposed in this study. Those circuits designed by the proposed Class AB systematic synthesis method have the advantages of Class AB circuit structure and translinear circuits. Two alternative design procedures were suggested for designing new circuits. Proposed synthesis technique is applied for designing of a first order all‐pass filter and a third order low‐pass filter. Circuits are simulated in PSpice using 0.35 µm CMOS technology parameters. Time domain and frequency domain analysis of the proposed filters are performed, and simulation results of those are also presented. The simulation results show that the proposed synthesis technique is appropriate for the design of different types of filters and has the advantages of Class AB circuit structure. Copyright © 2015 John Wiley & Sons, Ltd.     

Modeling and validation of high selective harmonic reduced bandpass filter using coupled resonators and defected ground structures

Recent developments in wireless communication systems demand good Band pass filter (BPF) with high quality factor and good selectivity to select the required signal from the adjacent signals. In this paper one coupled Band pass filter with centre frequency 2?GHz and 30?% Fractional Bandwidth (FBW) has been designed with rectangular split ring coupled resonators formed with conventional Microstrip transmission line. This designed BPF has been simulated with the help of MoM based IE3D electromagnetic EM simulation software. Here it is found that the proposed BPF provides second harmonic nearer to the twice of its passband centre frequency and some other few harmonics. Therefore, in this paper attention also has been given towards the suppression of harmonics with the help of Defected Ground Structures (DGS) in addition with the proposed coupled microstrip BPF. The proposed structure has been measured with Agilent vector network analyzer. There is a good agreement between simulated and measured responses.     

FABRICATION AND CHARACTERIZATION OF FULLY EMBEDDED DIPLEXER AND BAND-PASS FILTERS FOR ORGANIC RF SOP APPLICATIONS

ABSTRACT

In this paper, fully embedded dual-band WLAN diplexer, 2.4 GHz WLAN BPF and wide-band pass filter are investigated into a multi-layered organic package substrate for low cost RF SOP (System on Package) applications. These embedded passive components were designed and analyzed by using ADS circuit simulator and CST 3D EM simulator for verifying their applicability. The fabricated diplexer and filters are the smallest one of the filters formed onto the organic substrate. The diplexer has a size of 3 mm × 2.5 mm × 0.77 mm and exhibits an insertion loss of max ?0.68 dB in 2.4 ～ 2.5 GHz band and max –3 dB in 5.15 ～ 5.32 GHz band, respectively. The 2.4 GHz BPF has a size of 2.7 mm × 2.1 mm × 0.77 mm and exhibits an insertion loss of max ?2.7 dB. The WBPF has a size of 3.2 mm × 2.5 mm × 0.77 mm and exhibits an insertion loss of ?2.65 dB. The major benefit of these embedded passive components, compared to a discrete solution, is a significant simplification and size/volume reduction of RF systems design.     

Tunable Filters Based on Ferroelectrics

A novel microstrip tunable filter design approach is suggested. Coupling factor of a ferroelectric capacitor connected with the microstrip resonators of the filter is considered to make possible the design of the filter keeping constant the pass band width while tuning. Results of the filter characteristic simulation and measurement are presented.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.