VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers

An adaptive equalizer for ATSC standard HDTV receivers is developed and implemented in VLSI. This equalizer is based on the G-pseudo algorithm that combines the advantages of the decision directed and blind algorithms. It also conducts ghost cancellation for the reception of NTSC analog TV signals. A programmable error calculation unit is employed for a flexible implementation of several equalization algorithms. The filter coefficients have a long internal word-length for a satisfactory operation in the blind adaptation mode, but only parts of them are used for output calculation to reduce the hardware complexity. The performance of the system for seven GA reference channels is evaluated according to the adaptation algorithms, the number of delays for the adaptation, and the word-length of the filter coefficients. The chip area and power consumption according to the time multiplexing ratio are estimated.Wonyong Sung received the B.S. degree in electronic engineering from the Seoul National University in 1978, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST) in 1980, and the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 1987.From 1980 to 1983, he worked at the Central Research Laboratory of the Gold Star (currently LG electronics) in Korea. During his Ph.D. study, he developed parallel processing algorithms, vector and multiprocessor implementation, and low-complexity FIR filter design. He has been a member of the faculty of the Seoul National University since 1989. From May of 1993 to June of 1994, he consulted the Alta Group for the development of the Fixed Point Optimizer, automatic word-length determination and scaling software. From January of 1998 to December of 1999, he worked as a chief of the SEED (System Engineering and Design center) in Seoul National University. He was an associate editor of the IEEE Tr. Circuits and Systems II from 2000 to 2001, is a design and implementation technical committee member of the IEEE Signal Processing Society, and is a VLSI systems and application technical committee member of the IEEE Circuits and Systems Society. He was the general chair of the IEEE Workshop on Signal Processing Systems in 2003. He founded a venture company, Edumedia Technologies, in 2000, and has developed a handheld educational device for kids, SpeakingPartner, for mass production.His major research interests are the development of fixed-point optimization tools, implementation of VLSI for digital signal processing, and development of multimedia software for handheld devices and VLIW digital signal processors.Youngho Ahn received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Seoul, Korea, in 1997 and 1999 respectively. From 1999 to 2000, he was with Samsung Electronics, Kyunggi-Do, Korea, where he was involved in the ASIC design and development of ATSC digital television receivers. Since 2001, he has been with GCT Semiconductor, Inc., where he works in the communications IC design group. His research interests include wireless communications and ASIC design of communications systems.Eunjoo Hwang was born in Taegu, Korea on April 7, 1974. She received the B.S and M.S degrees in electrical engineering from Seoul National University in 1997 and 1999, respectively. Currently, she works for Silicon Image in Sunnyvale, California, USA as a digital circuit design engineer. Her research interests include blind equalization, joint timing recovery algorithm and storage network design.     

An Improved LZW Data Compression Algorithm and Its VLSI Implementation

Improved LZW algorithm was introduced. By adding a preprocessor to conventional LZW configuration for decreasing correlation between original data, the single large dictionary in conventional implementation was partitioned into a dictionary set that consisted of several small address space dictionaries. As doing so the dictionary set has small lookup time, and can operate in parallel. Besides, XOR-based hash function, which computed the dictionary index as the exclusive-or of the parent index and the present character, has been applied. Simulation results show that the improved algorithm has better compression ratio for image data than conventional LZW algorithm and DLZW （dynamic LZW） algorithm, and has competitive performance for text data with DLZW algorithm. The parallel VLSI implementation of the improved algorithm is proposed, and is realized using FPGA XC4VLX15-10. Experiment results show that the chip can yield a compression rate of 198.4 Mbytesis, it is about 6.9 times the compression rate of implementing conventional LZW, and 3.2 times the compression rate of implementing DLZW.     

Digital TV Receiver for NTSC Color TV Signals with Dual Word-Length DPCM Coding

A video codec system for carrying one broadcast quality NTSC color TV channel at a rate of 42.935 Mbits/s has been proposed. The receiver of the video codec system is developed for recovery of the original signal. The receiver accepts a 42.935 Mbits/s serial TDM data stream with a synchronous clock from the Transmitter. The receiver detects the unique sync code and inserts a horizontal blanking pattern which has been removed from the transmitting data. The audio and video data are separated at the outputs of the demultiplexer. The 4/8 bit dual length code word of the video data is smoothed out by a buffer memory and fed to the DPCM reconstruction loop. The analog NTSC color video signal as well as the audio signal are reconstructed after the D/A conversion. This paper describes the design and development of the receiver portion (Fig. 1) of the codec which is capable of transmitting'one color signal at broadcast standards on a T3 digital link.     

基于FPGA数字电视CA系统加密算法的实现

随着科学技术的发展,数字电视成为现代电视系统的主流.数字电视的关键是条件接收系统,条件接收系统中的关键性技术是要有加密技术的支持,加密技术关系到整个数字电视网络的安全性.而数字电视条件接收系统的核心问题是对加扰控制字的加密.为了确保电视信号安全有效的传输,加密技术是当下研究的热点之一.因此以下主要介绍基于FPGA数字电视条件接收系统中DES加密算法的实现,最后的仿真结果论证了该算法实现方案在条件接收系统中的可行性.     

Design of a DPCM codec for VLSI realization in CMOS technology

Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.     

Digital DPCM Codec for TV Signals Based onDeltaM/DPCMDigital Conversions

A digital differential pulse-code modulation (DPCM) codec based on ΔM/DPCM and DPCM/ΔM digital conversions is presented as an equivalent replacement of a conventional DPCM codec for TV signals by using digital processing technology. A generalized model and equivalent circuit are shown for the digital DPCM codec, and transfer characteristics and quantizing noises are analyzed. The digital DPCM codec is designed for 1-MHz TV signals and the performance is verified by experiments. By the use of double integration ΔM and digital filter technology, it is shown that at the ΔM sampling rate of 16 MHz the overall SNR performance is sufficiently good for use as a conventional DPCM codec, and the digital code converters can be realized with commercially available transistor-transistor-logic (TTL) medium-scale-integrated (MSI) circuits and low-power emitter-coupled-logic (ECL) integrated circuits (IC's).     

一种新型的数字电视音频压缩技术原理

介绍了目前数字电视音频的发展趋势,分析了高清晰数字电视音频的一种新型技术--aacplus/DTS,研究了该音频编解码器的结构和原理,展望了其应用前景.     

DES加密算法的VLSI实现方法

简述了DES加密算法的发展历史和核心思想,并给出了一种VLSI实现方法.并且在数据通道中采用了流水线结构,这样的结构比软件实现有着更好的加密性能.文中着重介绍了DES算法中的S-Box,替换和迭代过程.     

OFDM系统同步算法研究及其VLSI实现

针对正交频分复用（OFOM, Orthogonal Frequency Division Multiplex）无线传输系统,提出并设计了一种适用于802．11a标准前导序列的同步算法。首先基于接收基带数据能量判断信道空闲状态,再计算数据归一化自相关值检测帧起始位置,最后利用基带数据与参考训练序列的互相关运算检测OFDM符号的起始位置,实现同步功能。算法的硬件实现采用移位加和流水线技术来提高系统的性能与效率。实践表明,所提算法能有效地实现同步并且硬件实现复杂度低,适合于超大规模集成电路（VLSI,Very LargeScale Integration）的实现。     

论数字电视中数字音频的编码压缩技术

数字电视中的数字音频编码压缩技术。是根据人耳听阈的声心理学的基本特性提出的。人耳听阈的声掩蔽效应理论。使数字音频编码压缩技术得以应用和推广。本应用人耳听觉的声心理学对数字音频的编码压缩技术进行了详细的理论分析和论述。     

六边形运动估计算法的VLSI实现

运动估计是视频压缩中最重要的环节.在分析了六边形算法的基础上,给出了一种有效的数据流结构,并据此提出了一种全流水并行的整数像素运动估计实现电路,该电路结构能有效的减小对外部存储器的访问.综合后的电路能够稳定的工作在100MHz频率下,仿真实验证明,该VLSI结构完成一次块搜索平均需要140个周期,能满足HDTV实时编码的要求.     

高分辨模式数字脉压的时域算法及其利用FPGA的实现方法

雷达高分辨模式是针对目标架次的识别而设计的，它具有开窗采样和保留全脉压结果的特点。本文针对这一特点给出了一种新的时域数字脉压算法。这种算法通过数据和系数分别分段降低脉压阶数，既节省了硬件资源又具有实时性。最后给出了利用FPGA的具体实现方法。     

基于FPGA的数字脉冲压缩算法的设计与实现

介绍了雷达信号处理系统中脉冲压缩技术的现场可编程门阵列（FPGA ）实现方法,研究和分析了线性调频信号的脉冲压缩算法,结合研究目标和设计要求,设计了一种基于数据分段的脉冲压缩处理方法,通过SignalTap仿真证明了其有效性。     

一种改进的近似平方算法的VLSI实现

提出了一种适用于Viterbi算法的改进的近似平方算法--二阶近似算法.该算法最大相对误差(maximum relative error,MRE)和平均相对误差(average relative error,ARE)都非常低,与最新报道相比,MRE和ARE分别减小了20%和70%左右.同时,在0.6μm CMOS工艺条件下,实现了基于该算法的7-bit平方器,其延时和晶体管数与最新报道相当.     

一种改进的近似平方算法的VLSI实现

提出了一种适用于Viterbi算法的改进的近似平方算法——二阶近似算法.该算法最大相对误差( m aximumrelative error,MRE)和平均相对误差( average relative error,ARE)都非常低,与最新报道相比,MRE和ARE分别减小了2 0 %和70 %左右.同时,在0 .6 μm CMOS工艺条件下,实现了基于该算法的7- bit平方器,其延时和晶体管数与最新报道相当.     

数字电视压缩技术的研究与应用

本文着重研究了数字电视压缩及编码技术，并介绍数字电视技术今后的发展方向，提出了多媒体技术在信息传输中的重要作用。     

一种用于电视系统中的图像清晰度测量算法及实现

本文介绍了数字电视中用于增强图像画质的一种清晰度测量的方法,该方法使用图像中的频率信息、细节信息和局部图像的动态范围来判断当前输入的图像是一幅真实的高清图像还是在信号传输过程中被放大成高清信号的伪高清图像信号。从而利用得出的清晰度测量结果对真实高清图像信号和伪高清图像信号进行不同的清晰度和对比度调整。该方法的设计应用填补了数字电视图像后处理中对于原始信号检测的一个空白。本文介绍了该方法的基本原理和具体实现的算法,并讨论了该算法的硬件实现方案和代价。     

超高清数字电视视频压缩编码技术

超高清电视逐步成为相关研究领域的热点话题.然而,其特有的超高分辨率特点也造成了数据量的不断增大,传统的H.264/AVC视频编码标准已经不能满足超高清电视的高压缩比要求,亟需新的视频压缩编码技术.基于此,新一代HEVC视频图像编码标准被提出,其不仅能实现与H.264/AVC标准一致的视频质量,而且其视频流的码率也减少了...     

Wimax系统双二进制Turbo码的译码算法及VLSI实现

设计了一款应用于World Interoperability for Microwave Access (Wimax)系统的双二进制Turbo码译码器.该译码器对传统Max-log-MAP译码算法进行改进,在增加很少计算复杂度下有效地补偿了传统算法中max计算带来的误差.此外,提出了一种低复杂度,适用于Wimax系统中所有Turbo码码长的通用交织器结构.仿真结果表明,改进的Max-log-MAP译码算法在误码率10-4下相对于传统算法获得了约0.35~0.4 dB的译码增益;提出的通用交织器结构明显降低了译码器的计算复杂度和面积,提高了系统的吞吐率.该译码器可以在200 MHz工作频率下得到20.91 Mb/s的吞吐率,完全满足Wimax系统数据率的要求.     

数字电视机顶盒7710上图形显示GDP的实现

实现高清数字电视机顶盒的交互式功能,首先要实现其图形显示功能,介绍了在机顶盒7710上GDP图形显示的实现过程,可用相应的画图函数在GDP层上画出16位色的位图。