Design and Implementation of a Bandpass–Bandpass Diplexer Using Coupled Structures

Wireless Personal Communications - In this paper, a bandpass–bandpass two channels diplexer with operating frequencies of 1.7 GHz and 2.1 GHz is designed and fabricated on RT/duroid...     

An Active Recursive RF Filter in 0.35 μm BiCMOS

An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is ?26 and ?34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.     

Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

An ultra-wideband (3.1-10.6 GHz) low-noise amplifier using the 0.18 μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm2.     

Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

This paper presents a programmable multi-mode finite impulse response (FIR) filter implemented as switched capacitor (SC) technique in CMOS 0.18 μm technology. Intended application of the described circuit is in analog base-band filtering in GSM/WCDMA systems. The proposed filter features a regular structure that allows for elimination of some parasitic capacitances, thus significantly improving the filtering accuracy. Due to its modularity that allows for dividing the circuit into two separate sections, the circuit can be easily reconfigured to work as either infinite impulse response (IIR) or as finite impulse (FIR) filter. One of the key components that allows for this multi-mode operation is the proposed programmable and ultra low power multiphase clock circuit. The 24-taps filter for the sampling frequency of 30 MHz dissipates power of 4.5 mW from a 1.8 V supply.     

A Linear CMOS OTA and Its Application to a 3.3V 20MHz High-Q gm-C Bandpass Filter

A design of a linear and fully-balanced operational transconductance amplifier (OTA) with improved high DC gain and wide bandwidth is presented.Derivative from a single common-source field effect transistor (FET) cascade and its DC I-V characteristics,the third-order coefficient g3 has been well compensated with a parallel FET operated in the triode region,which has even-odd symmetries between the boundary of the saturation and triode region.Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters.A negative resistance load (NRL) technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes.Additionally,derivations from the ideal -90. phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest.HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply.As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0.18μm CMOS process with two kinds of gate-oxide layers,which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.     

Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented.The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver.The area and power are decreased greatly compared with other designs.The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video.The 0.18μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC,which occupies a 2.6×2.6 mm~2 area and consumes 83 mW under typical work modes.     

A 2.4 GHz power amplifier in 0.35 μm SiGe BiCMOS

This paper presents a 2.4 GHz power amplifier (PA) designed and implemented in 0.35 μm SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB, improving the stability and the gain of the circuit. In addition, a low-pass network for output matching is designed to improve the linearity and power capability. At 2.4 GHz, a P_(1dB) of 15.7 dBm has been measured, and the small signal gain is 27.6 dB with S_(11) < -7 dB and S_(22) < -15 dB.     

一种0.35 μm CMOS高精度Σ-Δ A/D转换器

提出了一种应用于MEMS压力传感器的高精度Σ-Δ A/D转换器。该电路由Σ-Δ调制器和数字抽取滤波器组成。其中,Σ-Δ调制器采用3阶前馈、单环、单比特量化结构。数字抽取滤波器由级联积分梳状(CIC)滤波器、补偿滤波器和半带滤波器(HBF)组成。采用TSMC 0.35 μm CMOS工艺和Matlab模型对电路进行设计与后仿验证。结果表明,该Σ-Δ A/D转换器的过采样比为2 048,信噪比为112.3 dB,精度为18.36 位,带宽为200 Hz,输入采样频率为819.2 kHz,通带波纹系数为±0.01 dB,阻带增益衰减为120 dB,输出动态范围为110.6 dB。     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

0.7-dB Insertion-Loss D-Band Lange Coupler Design and Characterization in 0.13 μm SiGe BiCMOS Technology

Design, measurement, and characterization of a low-loss Lange coupler on Si-substrate up to 170 GHz are presented in this paper. How to determine the value of the even number of the strip lines according to the process design rules is illustrated carefully based on odd- and even-mode impedance theory and calculation. The deembedding procedures of GSG pads and 50 Ω termination resistors are illustrated in details. Simulation and measurement results indicate that the fabricated on-chip 50 Ω resistors can be used for characterization of four-port Lange coupler by two-port network analyzer within expected measurement errors. Measurement results show that the minimum insertion loss of 0.7 dB at central frequency of 140 GHz is achieved, which is in excellent agreement with simulated data.     

A K-Band Low-Power Phase Shifter Based on Injection Locked Oscillator in 0.13 μm CMOS Technology

In this paper, the design challenges of the injection-locked oscillator (ILO)-based phase shifter are reviewed and analyzed. The key design considerations such as the operating frequency, locking range, and linearity of the phase shifters are analysed in detail. It is possible to optimize the phase shifter in certain parameters such as ultra-low power while meeting the requirements of a certain system. As a design example, a K-band phase shifter is implemented using a commercial 0.13 μm CMOS technology, where a conventional LC tank based topology is implemented but optimised with a good balance among power consumption, working range, sensitivity, and silicon area, etc. Measurement results show that the proposed phase shift is able to work at 22–23.4 GHz with a range of 180^° while consuming 3.14 mW from a 1.2 V supply voltage.     

Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.     

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier(TIA),which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 m CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency(RF) ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency(IF) bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure(NF) is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.     

基于0.35 μm工艺设计的APS CMOS图像传感器

介绍了一种基于CHRT公司0.35 μm工艺而设计的CMOS图像传感器.该图像传感器采用APS像素结构,像素阵列256×256,包含有列放大器、阵列扫描、串行接口、控制逻辑和ADC等模块.该图像传感器采用动态数字双采样(DDDS)的新方法消除FPN噪音,并已经通过MPW采用CHRT 0.35 μm salicide 2P4M工艺流片.     

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity(10Ω·cm) silicon substrate is presented.The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization.The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane.The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance.The simulated S11 is less than –10 dB over 46–95 GHz,which is well matched with the measured results over the available 40–67 GHz frequency range from our measurement equipment.A maximum gain of –5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansoft HFSS simulation.Compared with the current state-of-the-art devices,the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

Design and Simulation of a Broadband Bandpass Filter Based on Complementary Split Ring Resonator Circular “CSRRs”

Wireless Personal Communications - The aim of this article was to design CSRRs (complementary split ring resonator) miniaturized metamaterial cells. These cells should then be associated with...     

Design and Implementation of a Fast Switch Fabric

1　Introduction　ThereferencesystemlogicaldesignweconsiderinFig .1iscommonlyusedinhigh speedrouterimple mentation,suchasIBMQ64G[1～3] .Mostcarrier classpacket switchestodaysupport 8to 1 6linecards[4] ,andeachlinecardmaybefurthersubdivid edintomultiplesub ports.Forexample,anOC 48linecardmaybedividedintofourOC 1 2c ,sixteenOC 3externalinterfaces,etc .Sowepropose 1 6linecardsinourswitchfabricdesign .Mostcurrentre searchfocusesonhigh levelarchitecturalissuesonswitches,butseldomconsidersallth…