寄生电感对碳化硅MOSFET开关特性的影响

相比于传统的Si IGBT功率器件而言,碳化硅MOSFET可达到更高的开关频率、更高的工作温度以及更低的功率损耗.然而,快速的暂态过程使开关性能对回路的寄生参数更加敏感.因此,为了评估寄生电感对碳化硅MOSFET开关性能的影响,基于回路电感的概念,将栅极回路寄生电感、功率回路寄生电感以及共源极寄生电感等效成3个集总电感,并且从关断过电压、开通过电流及开关损耗等3个方面,对这3个电感对SiC MOSFET开关性能的影响进行了系统的对比研究.研究表明:共源极寄生电感对开关的影响最大,功率回路寄生电感次之,而栅极回路寄生电感影响最小.最后,基于实验分析结果,为高速开关电路的布局提出了一些值得借鉴的意见.     

Bridge-arm current reduction in DC-AC inverter

When building single-phase inverter with power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), switching action may cause poor reverse recovery characteristic due to body parasitic diode of MOSFET, which can produce peak current in the circuit loop and the high transient voltage and current (dv/dt, di/dt) during the turning-on period. In this article, a novel method to reduce the bridge arm current spike in DC-AC inverter is proposed. The presented method uses the improved and simplified coupled inductor which is connected between the upper and lower power devices. The parasitic capacitors of MOSFET are charged and discharged by the coupled inductor and the energy is released in the new loop; therefore, the bridge peak current is diminished. The time-domain model of transient-state analyses is given in detail. The current spike of the main switch is clamped efficiently. By increasing switching frequency, the volume of the magnetic core can be further reduced which is resulted from reduction in the reverse recovery current in parasitic diode. Because of the suppression of the spike current via the device, the switch-on loss of the power loss is reduced, and low on-state resistor of the power device can be adopted to suppress the conduction loss. The proposed approaches are validated with experimental results.     

采用分段式自适应PWM/PFM调制的Buck型DC-DC转换器设计北大核心

为了在轻重负载条件下获得更高的转换效率，采用分段式结构和导通电阻更小的NMOS作为输入级，并采用PWM/PFM双调制方式，设计了一种Buck型DC-DC转换器。为解决PWM/PFM调制信号切换问题，采用零电流检测方式进行切换。利用断续导通模式(DCM)和连续导通模式(CCM)下端NMOS管导通时电感电压的不同，检测下端NMOS在导通时电感电压大于零的周期。当电感电压大于零的周期大于2时，则处于DCM模式并自动采用PFM调制模式，关闭一部分功率管以减小开关频率和功率管寄生电容，优化轻载效率；反之则处于CCM模式并采用PWM调制。仿真结果表明，在负载电流10～1 000 mA范围内，该电路可以在两种调制模式平稳切换，在800 mA时峰值效率可提升到96%以上。     

Design of high-efficiency RF Class-D power amplifier

In this paper, the losses in a Class-D RF switching power amplifier and their frequency dependence are described. The losses analyzed are the switching, conduction, and gate drive losses. A 300 W, 13.56 MHz, Class-D circuit is designed in the traditional manner to illustrate the magnitude of the different types of loss. A circuit using the ZVS equations developed in this paper is designed. An experimental circuit is built using standard IRF540 devices in TO220 packages. That circuit does not meet its performance goals because of the package inductance. A new low inductance half-bridge package is introduced to solve this problem. Techniques for circuit layout and power measurements for RF applications are also presented in the experimental section. A low loss gate drive circuit is also presented using a Class-E circuit to provide the drive power. The experimental results confirm the accuracy of the design equations derived in this paper     

SiC和GaN电力电子器件的研究进展

与传统的Si基器件相比,SiC和GaN器件具有工作温度高、击穿电压高、开关速度快等优势,因此SiC和GaN材料是制备电力电子器件的理想材料。总结了近年来SiC和GaN电力电子器件的研究进展,包括二极管,MOSFET,JFET和BJT结构的SiC器件,以及SBD,PN结二极管,HEMT和MOSFET结构的GaN器件。     

An improved automotive power distribution system using nonlinearresonant switch converters

An improved automotive electrical system is proposed in which the generator is a high-efficiency AC machine connected to the battery by an AC-DC converter. The electrical loads are isolated from the battery by a DC-DC converter. This will allow gradual conversion to higher battery voltage, regulation of DC distribution voltage, and multiple distribution voltage levels. In the low-voltage, high-current, high-temperature environment of the automobile, in addition to packaging and thermal management, a major problem is the switching loss caused by leakage, package, and other parasitic inductances. The nonlinear resonant switch can remove this source of loss, achieving zero current switching without sacrificing conduction loss or MOSFET switch utilization. For the nonlinear resonant switch in a 1.5 kW load converter application, the upper limit is approximately 20 nH. Hence, device interconnections have low inductance, and MOSFET package inductances are taken into account. A low-voltage, high-current nonlinear resonant switch converter operating at 700 kHz an producing 600 W is described     

Low-voltage-swing monolithic dc-dc conversion

A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-/spl mu/m CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter.     

开关电源传导EMI仿真分析

随着电子技术的发展,电磁兼容性的研究越来越受到重视。文章以反激式开关电源为研究对象,分析并建立了MOSFET、变压器等元件的高频模型,利用电容、电感、变压器、MOSFET、功率二极管的高频模型组建了仿真电路。使用OrCAD10．5／PSpice软件模拟仿真,同时对其传导EMI进行了分析并提出了相应的抑制方法,这些工作对开关电源的电磁兼容性设计具有一定的指导作用。     

New high power DC-DC converter with loss limited switching and lossless secondary clamp

A new isolated high frequency high power DC-DC converter full bridge topology employing one resonant "soft" switching pole that is zero voltage switched and one phase-shifted hard switching pole with loss limited switching for primary switching is presented. The devices in the loss limited pole do not have resonant capacitors across them, but exhibit significantly lower losses than conventional hard switching as the energy dissipation is limited by the finite energy stored in the leakage inductance. This unique combination of zero voltage switching and loss limited switching reduces the switching loss in all primary devices to lower levels. Isolation is achieved by a coaxially wound high frequency transformer with ultra low leakage which increases throughput and efficiency. A novel nondissipative secondary rectifier clamp allows excellent control of reverse recovery energy. Converters that produce 128 kW at 25 kHz have been developed and are commercially available. As this topology exhibits complete control of all parasitic loss mechanisms, it can be easily scaled to higher power levels.     

基于CMOS工艺的太赫兹振荡器

在太赫兹频段,无源器件电容电感的品质因数低、电路的寄生参数以及MOS管的截止频率影响使太赫兹振荡器电路难以实现高功率输出。提出一种300 GHz可调谐振荡器,首先,采用改进的交叉耦合双推(Push-Push)振荡器结构,通过输出功率叠加的方法输出二次谐波300 GHz信号,增加了振荡器的输出功率并突破了MOS管截止频率,并通过增加栅极互连电感增加输出功率。其次,太赫兹振荡器摒弃传统片上可变电容调谐的方式,通过调节MOS管衬底电压改变MOS管的栅极寄生电容实现频率调谐,避免太赫兹频段引入低Q值电容,进一步增加了输出功率。提出的太赫兹振荡器采用台积电40 nm CMOS工艺,基波工作频率为154.5 GHz,输出二次谐波为 309.0 GHz,输出功率可达-3.0 dBm,相位噪声为-79.5 dBc/Hz@1 MHz,功耗为28.6 mW,频率调谐范围为303.5~315.4 GHz。     

埋氧沟槽栅双极模式JFET的仿真与实验

提出了埋氧沟槽栅双极模式JFET (BTB-JFET) ,其在栅极区域下面添加埋氧以减小栅漏电容Cgd. 首次通过仿真对包括BTB-JFET、常规的无埋氧层的沟槽栅双极模式JFET (TB-JFET）和现在正在广泛应用的Trench-MOSFET (T-MOSFET）等20V级的功率开关器件在高频应用时的功率损耗进行了比较,得到有重要意义的结论. 采用阻性负载电路. 仿真结果表明,与T-MOSFET和常开型TB-JFET 相比,常开型BTB-JFET在1MHz时开关功耗分别降低了37%和14%. 进行实验以证明仿真工作的合理性,首次成功地制造出常开型BTB-JFET和TB-JFET,其中埋氧结构是通过热氧化的方法实现的. 实验结果表明,与TB-JFET相比,在源漏零偏压时,BTB-JFET的Cgd减小了45%;在1MHz时,其开关时间与开关功耗分别降低了约7.4%和11%. 因此常开型BTB-JFET应是今后低压高频功率开关器件的研究发展方向.     

A self-driven soft-switching voltage regulator for future microprocessors

In conventional high frequency 12-V input voltage regulators (VR), large gate driver loss and body diode conduction loss raise crucial challenges to its gate driver implementation. The proposed self-driven topologies are basically buck-derived multiphase interleaving soft switching topologies, which eliminate the synchronous rectifier MOSFET drivers and save driving loss and body diode loss, so that it is a high efficiency, high power density solution for future microprocessors. A 1U four-phase 1.3-V/100-A VRM running at 1MHz demonstrates its advantages (cost, size and efficiency) over the conventional multiphase buck converter.     

一种新型软开关BUCK变换器

根据传统硬开关电源引起的不良影响,提出了一种新型软开关BUCK变换器,使得高低桥MOSFET管都能在不管是轻负载或者重负载情况下达到ZVS状态.在连续导电模式（CCM）和高负载电流情况下,上桥MOSFET管开通,下桥MOSFET管侧的二极管在死区时间内导电,这样就造成了上桥MOSFET管的开关损耗.新型软开关BUCK变换器在传统BUCK变换器的基础上加入了电感和电容,在外加电感电容的情况下,在CCM下的死区时间内的电感电流可以有效地从下桥二极管整流到上桥二极管中.根据仿真结果和工作模式分析验证其性能.     

Class DE current-source parallel resonant inverter

This paper introduces a Class DE current-source parallel resonant inverter, along with its design procedure and experimental results. This circuit offers several desirable features. First, the proposed circuit lacks harmonic components of input current over the voltage-source inverters. Second, the source pin of the MOSFET is directly connected to the ground, so that it is not necessary to use a complicated gate-drive circuit. Third, by maintaining zero-current switching, power loss by the parasitic inductor at turn-off decreases. The measured efficiency is over 90% at the output power of 3.5 W and the operating frequency of 0.5 MHz     

A Practical Switching Loss Model for Buck Voltage Regulators

In this paper, a review of switching loss mechanisms for synchronous buck voltage regulators (VRs) is presented. Following the review, a new simple and accurate analytical switching loss model is proposed for synchronous buck VRs. The model includes the impact of common source inductance and switch parasitic inductances on switching loss. The proposed model uses simple equations to calculate the rise and fall times and piecewise linear approximations of the high-side MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss in a synchronous buck VR. A simulation program with integrated circuit emphasis (Spice) simulations are used to demonstrate the accuracy of the voltage source driver model operating in a 1-MHz synchronous buck VR at 12-V input, 1.3-V output. Switching loss was estimated with the proposed model and compared to Spice measurements. Experimental results are presented to demonstrate the accuracy of the proposed model.     

Optimal Design of Resonant Gate Driver for Buck Converter Based on a New Analytical Loss Model

In this paper, the advantages of a new resonant driver are verified thoroughly by the analytical analysis, simulation and experimental results. A new accurate analytical loss model of the power metal oxide semiconductor field effect transistor driven by a current-source resonant gate driver is developed. Closed-formed analytical equations are derived to investigate the switching characteristics due to the parasitic inductance. The modeling and simulation results prove that compared to a voltage driver, a current-source resonant driver significantly reduces the propagation impact of the common source inductance during the switching transition at high (>1 MHz) switching frequency, which leads to a significant reduction of the switching transition time and the switching loss. Based on the proposed loss model, a general method to optimize the new resonant driver is proposed and employed in the development of a 12 V synchronous buck voltage regulator (VR) prototype at 1 MHz switching frequency. The level-shift circuit and digital implementation of complex programmable logic device (CPLD) are also presented. The analytical modeling matches the simulation results and experimental results well. Through the optimal design, a significant efficiency improvement is achieved. At 1.5 V output, the resonant driver improves the VR efficiency from 82.7% using a conventional driver to 86.6% at 20 A, and from 76.9% using a conventional driver to 83.6% at 30 A. More importantly, compared with other state of the art VR approaches, the new resonant driver is promising from the standpoints of both performance and cost-effectiveness.     

MOSFET器件并联实验研究

采用图腾柱的驱动方式,设计了应用于IXYS公司的功率MOSFET器件DE375-102N12的驱动电路。单个开关在多脉冲下具有良好的脉冲一致性。以该功率MOSFET器件进行的6个并联实验说明,影响并联的MOSFET的动态均流的主要参数是放电回路中的回路电感和寄生电感,电路板的布局与布线对并联的功率MOSFET有很大的影响,良好的布局可以大大提高电路的性能。     

一种新型SiC SBD的高温反向恢复特性

与传统硅基功率二极管相比,碳化硅肖特基势垒二极管(SiC SBD)可提高开关频率并大幅减小开关损耗,同时有更高的耐压范围.设计并制作了具有场限环结终端和Ti肖特基接触的1.2 kV/30 A SiC SBD器件,研究了该SiC SBD在100~300℃时的反向恢复特性.实验结果表明,温度每上升100℃,SiC SBD反向电压峰值增幅为5%左右,而反向恢复电流与反向恢复时间受温度影响不大;温度每升高50℃,反向恢复损耗功率峰值降低5%.实验结果表明该SiCSBD在高温下能够稳定工作,且具有良好的反向恢复特性,适用于卫星、航空和航天探测、石油以及地热钻井探测等需要大功率、耐高温和高速器件的领域.     

PWM zero-voltage switching boost-derived converters with outputisolation

In this paper, the basic operations and steady-state analysis for three modified boost-derived power converter topologies are presented. Unlike the conventional boost topology, these power converters provide electrical isolation and zero-voltage switching, while having identical component stresses as those in the conventional boost power converters. Zero-voltage switching and proper transformer-core resetting are achieved from the resonance that occurs between the parasitic capacitance of the power switch and the transformer magnetizing inductance. By introducing a lossless clamping circuit, the voltage stresses across the switching devices are limited to the reflected output voltage to the primary side     

Design of Parasitic Inductance Reduction in GaN Cascode FET for High‐Efficiency Operation

This paper presents a method of parasitic inductance reduction for high‐speed switching and high‐efficiency operation of a cascode structure with a low‐voltage enhancement‐mode silicon (Si) metal–oxide–semiconductor field‐effect transistor (MOSFET) and a high‐voltage depletion‐mode gallium nitride (GaN) field‐effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.