32位快速乘法器设计

本文介绍了一种通过符号位扩展,可以分别完成32位有符号/无符号二进制数乘法的高性能乘法器设计。该乘法器采用高基Booth算法,简化部分积的符号扩展,通过采用较之常规Wallace树具有更规则和更简洁的连接复杂度的阵列结构以及一种新型超前进位加法器来进一步提高乘法器的运算速度。整个设计采用4级流水线结构,在FPGA上进行了验证,并成功地应用于时/频联合均衡器工作中。     

Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits

In this paper we develop dynamic models for ideal three- and four-stage voltage multipliers. Starting from the models proposed, we can perform a pencil-and-paper area-efficient optimized design. The circuits discussed are commonly used in power ICs or memory ICs to allow the switching on of an MOS device. The models proposed are validated both by measurement on a breadboard and by SPICE simulation.     

Monte Carlo simulation of nanoelectronic devices

The Monte Carlo simulation method is used to analyze the behavior of electron and hole mobility in different nanoelectronic devices including double gate transistors and FinFETs. The impact of technological parameters on carrier mobility is broadly discussed, and its behavior physically explained. Our main goal is to show how mobility in multiple gate devices compares to that in single gate devices and to study different approaches to improve the performance of these devices. Simulations of ultrashort channel devices taking into account quantum effects are also shown.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.     

HIPS与ABS塑料性能的对比分析

本文从不同温度实验、氙灯老化实验、紫外光老化实验三个方面对比分析了ABS及HIPS的性能,指出用HIPS注塑的成品,相比ABS注塑的成品,各方面的品质相差甚远,并由此得出在家电产品的降成本过程中,慎用HIPS取代ABS生产塑料零配件.     

A rigorous design method for binary cellular neural networks

In order to be able to take full advantage of the great application potential that lies in cellular neural networks (CNNs) we need to have successful design and learning techniques as well. In almost any analogic CNN algorithm that performs an image processing task, binary CNNs play an important role. We observed that all binary CNNs reported in the literature, except for a connected component detector, exhibit monotonic dynamics. In the paper we show that the local stability of a monotonic binary CNN represents sufficient condition for its functionality, i.e. convergence of all initial states to the prescribed global stable equilibria. Based on this finding, we propose a rigorous design method, which results in a set of design constraints in the form of linear inequalities. These are obtained from simple local rules similar to that in elementary cellular automata without having to worry about continuous dynamics of a CNN. In the end we utilize our method to design a new CNN template for detecting holes in a 2D object. © 1998 John Wiley Sons, Ltd.     

复合绝缘子表面憎水性和污秽对其湿闪电压的影响

提出一种染污复合绝缘子的湿闪络试验方法，给出不同憎水性和污秽条件下复合绝缘子的干、湿闪电压，并根据试验结果对其干、湿闪机理进行了分析。试验结果表明：复合绝缘子的湿闪电压随表面憎水性的减弱而降低，干闪电压与表面憎水性无关；表面存在污秽时，绝缘子的湿闪电压较清洁表面有明显下降；其表面憎水性的不同仍然影响着复合绝缘子的湿闪电压；在不同盐密条件下，涂污的复合绝缘子湿闪电压也随表面憎水性的减弱而降低；重污秽条件下其表面憎水性较差时的湿闪电压要比憎水性良好时下降11％。     

机车蓄电池性能监测仪的研究与设计

介绍一种基于ARM芯片的机车蓄电池性能监测仪的设计。该蓄电池性能监测仪能够完成2、4、6和12 V单体电池和蓄电池组的核对性放电实验,能够对蓄电池容量进行快速测量,能够停电后在线监测蓄电池容量及充电电压检测。通过上位机,还可以完成蓄电池测试数据的管理。测试精度高、操作简单灵活、可靠性高。     

车用微电机性能的优化设计

本文分析了汽车后视镜电机使用中的种种问题,其中部分原因来自于微电机的性能。而汽车微电机在设计中,磁瓦的尺寸形状对电机性能有非常重要的影响,等厚磁瓦引起电机振动噪声变大、电流波形差、电刷放电大、性能不稳定等问题,本文通过电机的理论分析,提出了三种偏心的设计方法,通过实验,比较和分析了不同偏心磁瓦对电机性能的影响,通过波形分析和性能比较,验证了分析结果的正确性和可行性,对于车用微电机的设计有一定的指导意义。     

洗衣机性能测试恒温水系统设计

本文介绍了为家用洗衣机性能测试实验室而设计的恒温水供水系统。该系统可为六工位家用电动洗衣机提供5℃~60℃、误差不超过±0.3℃的恒温水。供水压力0.24MPa、误差不超过±0.02MPa。电热水器及风冷冷水机组联合使用控制水温。在恒温水箱和冷水机组之间设置板式换热器,保证恒温水箱温度的精确恒定。为了保证水系统各处温度相同的同时避免供水水泵的频繁启停,冷温水与热水系统分别采用独立自循环的方式。变频供水水泵不仅可以调节水流量大小,而且可以精确控制供水水压。依据GB/T 5750.4-2006与GB/T 4288-2008标准对水质进行严格软化处理,保证洗衣机用水对其性能测试结果无影响。联合使用PLC和PID,测试精度较传统恒温水系统更高。     

板栅尺寸及结构对电池放电性能的影响

研究了板棚的外形尺寸、筋条结构及极耳位置对汽车用蓄电池放电性能的影响。     

动力锂离子电池组充电器设计与性能监测

锂离子电池作为一种新型环保电池,在便携式设备中得到了很好的推广应用,并被认为是未来电动汽车的动力源.同时动力锂离子电池由于自身特点,对充电系统提出很高的要求.从安全性、均衡性、可靠性、经济性以及多方面考虑,提出了一种采用并联充电、串联放电的动力锂离子电池组充电器拓扑结构,并通过实验数据进行了分析论证.通过RS232串口建立了充电器与PC机的数据通道.既实时显示每一节单体电池的充电状态,又可以作为充电器的质量检验和故障诊断的手段.用实测数据进行了验证.结果表明,该充电装置很好地满足了充电要求.     

某型无人机气囊系统设计及动态性能测试

为实现某型无人机的安全回收,需设计一种新型气囊来吸收无人机着陆时的冲击过载,防止无人机内部的电子设备受到损伤。首先完成了气囊囊体的设计,然后通过NIPAC架构下的PXI系统模拟无人机着陆过程中的气囊缓冲过程,同时采集气囊的各项动态性能参数,为气囊的设计与改进提供了必要的实验数据。试验结果表明,所设计的气囊符合设计要求。     

基于UML的电力通信网管的性能分析与设计

对新一代电力通信网网管系统的应用、性能及结构进行了分析和探讨，然后在此基础上选用了UML（统一建模语言）对系统进行建模，最后说明了UML模型、IDL及CORBA中间件之间的关系。     

不同粒径的Zr-MOF的制备及性能

采用简单的溶剂热法制备不同颗粒大小的锆基金属有机框架材料(MOF)。XRD和SEM分析结果表明:与Zr-MOF相比,纳米Zr-MOF的颗粒更小,直径约为100 nm;循环伏安、恒流充放电测试研究电化学性能。在6 mol/L KOH中,在扫描速率为5 m V/s,电位范围分别为-0.10~0.50 V和-0.15~0.60 V时,Zr-MOF和纳米Zr-MOF电极材料的比电容分别为135 F/g和1 144 F/g。在电流为0.005 A,电压窗口分别为-0.10~0.40 V和-0.15~0.35 V时,进行恒流充放电测试,纳米Zr-MOF拥有更好的电容性能。     

The complex binary number system

Conversion algorithms and arithmetic procedures for a (-1 + j)-base binary number allow a given complex number to be represented as one unit. This should simplify the operations involving complex numbers in today's microprocessors. With the division process secure, we can implement the usual algorithms for calculating functions and processes such as logarithms, exponentials and trigonometric functions Currently, work is underway to write Java applets for the algorithms. We are planning to design an arithmetic unit based on the new binary system which will then be implemented using field programmable gate arrays     

薄壁装配单元并联结构设计及性能分析

薄壁件由于结构复杂刚性差且精度要求高,薄壁件装配主要由人工完成。存在自动化程度低、产品良率低、效率差、严重依赖工人的技术水平的问题。为了提高产品质量和生产效率,急需采用自动化装配设备。薄壁件的装配单元需要根据在线测量数据分类匹配装配,采用传统的工业机器人,占用较大的工作空间,并联机器人结构柔性,占用空间小,本文设计提出一种薄壁件自动化分拣装配单元设计方案,来代替传统人工分拣与装配的生产方式。首先根据薄壁件分类装配功能需求,设计了并联结构,建立了并联结构的动力学模型和运动学模型;分析了并联结构快速运动时速度及加速度的变化规律,3条主动臂和中间支链的角度数据曲线变化平稳,没有发生突变,角速度和角加速度相对平稳,保证了测量相机工作精度,并联机构的稳定性满足设计要求;动平台的位移曲线与预定轨迹重合,结果显示所设计的机构可以满足功能要求。该结构工作空间小,可以实现薄壁件装配的自动化,保证了产品的质量。     

基于LCL滤波器的并网/独立双模式控制高性能逆变器的设计与并联技术研究

基于LCL滤波器,设计并实现了既可工作在并网模式﹑又可工作在独立供电模式的高性能通用单相逆变器,设计了两种模式下的比例谐振(PR)控制器,既消除了系统输出的稳态误差,又保证了系统良好的动态性能.在此基础上进行了逆变器并联技术的研究,基于CAN总线实现了输出同步及并联均流,给出了系统总体结构和具体实现.5 kW的样机实验结果验证了理论分析和控制策略的有效性.     

Influence of electrical insulation on design and performance ofpower equipment

The potential impact of research and development on new dielectric materials on high-voltage designs for transformers, capacitors, generators, and SF₆-insulated equipment is reviewed in the context of limitations imposed by present tests and material properties. The potential technical and economic benefits of new dielectric systems are described and directions indicated for future research and development. The following impacts on power equipment are anticipated: improved reliability, electrical performance and economics of most systems, improved mechanical performance of generators and transformers, improved thermal rating of transformers and cables, and a positive environmental impact for transformers and capacitors