A Ka-band low-noise amplifier with a coplanar waveguide (CPW) structure with 0.15-μm GaAs pHEMT technology

This investigation explores a low-noise amplifier (LNA) with a coplanar waveguide (CPW) structure, in which a two-stage amplifier is associated with a cascade schematic circuit, implemented in 0.15-μm GaAs pseudo-morphic high electron mobility transistor (pHEMT) technology in a Ka-band (26.5-40.0 GHz) microwave monolithic integrated circuit (MMIC). The experimental results demonstrate that the proposed LNA has a peak gain of 12.53 dB at 30 GHz and a minimum noise figure of 3.3 dB at 29.5 GHz, when biased at a V_(ds) of 2 V and a V_(gs) of-0.6 V with a drain current of 16 mA in the circuit. The results show that the millimeter-wave LNA with coplanar waveguide structure has a higher gain and wider bandwidth than a conventional circuit. Finally, the overall LNA characterization exhibits high gain and low noise, indicating that the LNA has a compact circuit and favorable RF characteristics. The strong RF character exhibited by the LNA circuit can be used in millimeter-wave circuit applications.     

A low power 2.5-5 GHz low-noise amplifier using 0.5-μm GaAs pHEMT technology

正A two-stage 2.5-5 GHz monolithic low-noise amplifier(LNA) has been fabricated using 0.5-μm enhanced mode AlGaAs/GaAs pHEMT technology.To achieve wide operation bandwidth and low noise figure,the proposed LNA uses a wideband matching network and a negative feedback technique.Measured results from 2.5 to 5 GHz demonstrate a minimum of 2.4-dB noise figure and 17-dB gain.The input and output return loss exceeded -10-dB across the band.The power consumption of this LNA is 33 mW.According to the author's knowledge,this is the lowest power consumption LNA fabricated in 0.5-μm AlGaAs/GaAs pHEMT with the comparable performance.     

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35?µm CMOS high-frequency model to design a fully integrated 1?V, 5.2?GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50?Ω. The simulation results show that the amplifier provides a gain of 9.48?dB, a noise figure of 4.08?dB, and draws 13.4?mW from a 1?V supply. The S11 and S22 are both lower than ?15?dB.     

Design of a low noise distributed amplifier with adjustable gain control in 0.15μm GaAs PHEMT

正A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor(PHEMT) technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point(IIP3),which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm~2.     

A 50 MHz-1 GHz high linearity CATV amplifier with a 0.15μm InGaAs PHEMT process

A 50 MHz-1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit (MMIC) for cable TV is presented.A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity.A novel DC bias feedback is introduced to stabilize the operation point,which improved the linearity further.The circuit was fabricated with a 0.15μm InGaAs PHEMT (pseudomorphic high electron mobility transistor) process.The test was carried out in 75Ωsystems from 50 MHz to 1 GHz.The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than±1dB.An excellent noise figure of 1.7-2.9 dB is obtained in the designed band.The IIP3 is 16 dBm, which shows very good linearity.The CSO and CTB are high up to 68 dBc and 77 dBc,respectively.The chip area is 0.56 mm~2 and the power dissipation is 110 mA with a 5 V supply.It is ideally suited to cable TV systems.     

一种基于0.15μm GaAs pHEMT工艺的Ka波段功率放大器设计

基于0.15μm GaAs pHEMT工艺设计了一款Ka波段AB类功率放大器.该功率放大器对匹配网络中的通孔电容设计进行改进.将改进式通孔电容运用于功合器设计中.此项改进使输出级功合器的插入损耗改善了0.8~3dB, 提高了功率合成效率.测试结果显示, 此功率放大器在33-37GHz工作频率内, 实现了31±1dB的小信号增益, 饱和输出功率大于31.18dBm, 功率附加效率(PAE)大于21.7%.       

An asymmetric broad waveguide structure for a 0.98-μm high-conversion-efficiency diode laser

A novel asymmetric broad waveguide diode laser structure was designed for high power conversion efficiency (PCE). The internal quantum efficiency, the series resistance, and the thermal resistance were theoretically optimized. The series resistance and the thermal resistance were greatly decreased by optimizing the thickness of the P-waveguide and the P-cladding layers. The internal quantum efficiency was increased by introducing a novel strain-compensated GaAs0.9P0.1/InGaAs quantum well. Experimentally, a single 1-cm bar with 20% fill factor and 900 μm cavity length was mounted P-side down on a microchannel-cooled heatsink, and a peak PCE of 60% is obtained at 26.3-W continuous wave output power. The results prove that this novel asymmetric waveguide structure design is an efficient approach to improve the PCE.     

An asymmetric broad waveguide structure for a 0.98-μm high-conversion-efficiency diode laser

A novel asymmetric broad waveguide diode laser structure was designed for high power conversion efficiency（PCE）.The internal quantum efficiency,the series resistance,and the thermal resistance were theoretically optimized.The series resistance and the thermal resistance were greatly decreased by optimizing the thickness of the P-waveguide and the P-cladding layers.The internal quantum efficiency was increased by introducing a novel strain-compensated GaAs0.9P0.1/InGaAs quantum well.Experimentally,a single 1-cm bar with 20% fill factor and 900 μm cavity length was mounted P-side down on a microchannel-cooled heatsink,and a peak PCE of 60% is obtained at 26.3-W continuous wave output power.The results prove that this novel asymmetric waveguide structure design is an efficient approach to improve the PCE.     

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process

An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.     

A 77-100 GHz power amplifier using 0.1-μm GaAs PHEMT technology

A wideband MMIC power amplifier at W-band is reported in this letter. The four-stage MMIC, developed using 0.1 μm GaAs pseudomorphic HEMT (PHEMT) technology, demonstrated a flat small signal gain of 12.4±2 dB with a minimum saturated output power (Psat) of 14.2 dBm from 77 to 100 GHz. The typical Psat is better by 16.3 dBm with a flatness of 0.4 dB and the maximum power added efficiency is 6% between 77 and 92 GHz. This result shows that the amplifier delivers output power density of about 470 mW/mm with a total gate output periphery of 100 μm. As far as we know, it is nearly the best power density performance ever published from a single ended GaAs-based PHEMT MMIC at this frequency band.     

A 6-bit 3-Gsps ADC implemented in 1μm GaAs HBT technology

The design and test results of a 6-bit 3-Gsps analog-to-digital converter （ADC） using 1 μm GaAs het- erojunction bipolar transistor （HBT） technology are presented. The monolithic folding-interpolating ADC makes use of a track-and-hold amplifier （THA） with a highly linear input buffer to maintain a highly effective number of bits （ENOB）. The ADC occupies an area of 4.32 × 3.66 mm2 and achieves 5.53 ENOB with an effective resolution bandwidth of 1.l GHz at a sampling rate of 3 Gsps. The maximum DNL and INL are 0.36 LSB and 0.48 LSB, respectively.     

Delta-sigma modulator with a 50-MHz sampling rate implemented in 0.18-μm CMOS technology

The results are presented of a design effort concerned with a delta-sigma modulator with a 50-MHz clock rate and a 128 oversampling ratio. Its prototype is fabricated in 0.18-μm CMOS technology and is powered by a 1.8-V unipolar supply. It provides a 9-bit resolution, while consuming 33 mW of power.     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

1D GaAs Detector Arrays for Digital X-ray Imaging with a 108-μm Spatial Resolution

A 1D x-ray detector array of pitch 108 m is designed, fabricated, and tested. The array is based on the p⁺–n–n–n⁺ structure made in epitaxial GaAs technology. Guard rings are incorporated to reduce detector cross coupling. It is announced that the technology proposed will be used to make arrays with a pitch of 50 m and a spatial resolution of 10 line-pairs/mm, suitable for digital mammography.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24–7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of ?107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40–51 mA from the 1.8-V supply and occupies an area of 440 μm ×  430 μm.     

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.