Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I _ON/I _OFF.     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

I-V characteristics of a ferroelectric field effect transistor

Abstract

There are many possible uses for ferroelectric field effect transistors. To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a FFET are described from empirical data. The effective gate capacitance and charge are derived from experimental data on an actual ferroelectric transistor. A general equation ^[1] for a MOSFET is used to derive the internal characteristics of the transistor. Experimental data derived from a Radiant Technologies^[2] FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations.

The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material. Two polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse. The transistor is also simulated using a mathematical model from earlier research ^[3]. This model accurately predicts the I-V characteristics of the transistor.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

A compact modelling of double-walled gate wrap around carbon nanotube array field effect transistors

The effects of multi-walled CNTs and array of channels are combined to form Double-walled Gate Wrap Around Carbon Nano Tube array Field Effect Transistor (DWGWA CNTFET). Numerical model is proposed for the device to study its performance. Screening and imaging effects of adjacent and inter walls in array of channels are included for calculating the drive capacitance, subsequently the drive current. This model suits for a wide range of chiralities and diameters. The change in drive capacitance of double-walled and single-walled device with respect to various drain and gate voltage for different values of number of channels, diameters are studied. The number of channels, CNTs diameters, chiralities of the tubes, source/drain length are varied and the corresponding responses of drive current, cut off frequency, signal delay time for both double and single walled devices are compared. In all cases, DWGWA CNTFET excels in its performance over Single-walled Gate Wrap Around Carbon Nano Tube array Field Effect Transistor (SWGWA CNTFET).The model of the proposed device can be utilized for designing the Nano devices with high power and high speed capability.     

一种基于保角映射的考虑端部效应的准三维轴向磁通电机磁场解析模型

轴向磁通永磁电机气隙磁场三维分布不均,且在电机内、外径处端部效应明显,应建立三维磁场模型来进行电机性能分析,而三维有限元计算十分耗时,因此需建立(准)三维气隙磁场解析模型.现有的考虑端部效应的AFPMMs气隙磁场解析模型,大多基于三维FEM辅助建模或等效磁路的方法,存在耗时过多或建模精确度不高的问题.针对以上不足,建立...     

A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance

Over the years, the approach of cylindrical gate MOSFETs has attracted several research initiatives due to the very inherent benefit of the cylindrical geometry over other conventional planar structures. Nowadays, the present boon in the research field of nanoscale device physics is attributed to a large extent by the development of junctionless devices. In our current research endeavor, we have for the first time proposed a new idea by incorporating the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate into a junctionless cylindrical gate MOS structure, thereby presenting a new device structure, a junctionless work function engineered gate cylindrical gate MOSFET (JL WFEG CG MOSFET). We have presented a rigorous analytical modeling of the proposed JL WFEG CG MOS structure by solving the two dimensional Poisson’s equation in cylindrical co-ordinates. Based on this analytical modeling, an overall performance comparison of the proposed JL WFEG CG MOS and normal JL CG MOS structure has been investigated in order to testify the improved performance of the proposed JL WFEG CG structure over its normal JL CG equivalent in terms of reduced short channel effects, threshold voltage roll off, drain induced barrier lowering and superior current driving capability. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

Atomistic modeling of the electrostatic and transport properties of a simplified nanoscale field effect transistor

A first-principle model is proposed to study the electrostatic properties of a double-gated silicon slab of nano scale in the framework of density functional theory. The applied gate voltage is approximated as a variation of the electrostatic potential on the boundary of the supercell enclosing the system. With the electron density estimated by the real space Green’s functions, efficient multigrid and fast Fourier-Poisson solvers are employed to calculate the electrostatic potential from the charge density. In the representation of localized SIESTA linear combination of atomic orbitals, the Kohn-Sham equation is established and solved self-consistently for the wavefunction of the system in the local density approximation. The transmission for ballistic transport across the atomic silicon slab at small bias is calculated. The charge distribution and electrostatic potential profile in the silicon slab versus the gate voltage are then analyzed with the help of the equivalent capacitive model. Quantum confinement and short gate effects are observed and discussed.     

A method of design for a class of 2-D filters

This paper discusses a method of designing quadrantally symmetric cascaded two-dimensional (2-D) digital recursive filters by subjecting a one variable approximating function to successive transformations. the needed approximation is done in the one variable domain rather than in the 2-D domain, hence leading to a large reduction of computational labour. Using cepstral techniques each denominator polynomial is spectrally factorized into recursible non-symmetric half plane components. A significant feature of the method is in decoupling the problems of approximation and stability. Consequently spectral factorization needs to be performed only once for each denominator polynomial. Effects of truncation on filter stability are minimized by ensuring rapid convergence of cepstra. the choice of an adequate DFT size in cepstral computations is shown to be an important consideration for many problems associated with spectral decomposition. Attempts are also made to stabilize the unstable transfer function using an existing 2-D discrete Hilbert transform method. Considerable distortion in magnitude characteristics is shown to result on stabilization. Finally the method is illustrated by two examples.     

开关电源近场辐射效应分析与模型研究

本文实验考察了一台功率因数校正器(PFC)主电路产生的辐射电磁场对传导干扰发射的影响,细致分析了PFC与EMI滤波器、电源输入线缆间的电磁耦合效应,在此基础上,建立了包含电场耦合效应的传导干扰电路模型并加以验证。基于电源共模传导干扰简化模型,提出了临界耦合距离概念并进行了实测,该参数可为开关电源早期阶段的EMC布局设计提供参考。最后,提出了几种辐射效应抑制新措施。