A self-consistent model for short-channel mosfets

A de model for short-channel MOSFETs is presented in this paper. Several second-order effects associated with small-geometry MOSFETs such as mobility degradation, carrier velocity saturation and channel length modulation are included in the model. The analysis emphasizes the modeling of the output conductance and the transconductance which are important in analogue circuit simulation. The theoretical predictions of the model are in good agreement with the experimental data available in the literature.     

3D analytical modeling of surface potential,threshold voltage,and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage \((V_{\mathrm{T}})\) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on \(V_{\mathrm{T}}\) and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.     

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Compact model and circuit simulations for asymmetric, independent gate FinFETs

We present a rigorous surface-potential-based compact model of independent-gate asymmetric FinFETs enabled by solving several long-standing theoretical problems. The model is verified with TCAD simulations and is implemented in a standard circuit simulator. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric FinFETs.     

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.     

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson’s equation using “variable separation technique”. The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.     

硅太阳电池模型参数的一种解析方法

通过对硅太阳电池的数学模型进行分析,给出了一种利用硅太阳电池的开路电压、短路电流以及最大输出功率点处的电压、电流确定模型参数的方法.对两种硅太阳电池进行了仿真及实验测量.数据分析结果表明该方法确定的模型能够反映硅太阳电池的特性.     

A 3D analytical modeling of tri-gate tunneling field-effect transistors

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.     

表征开口式电流互感器工作原理的解析模型

传统电流互感器一般采用闭磁路铁心设计,但受铁心材料存在磁饱和的限制,其在一次电流回路发生短路故障时,出现的直流电流分量会严重影响电流互感器的性能,导致其测量电流值的误差可能非常大。开口式电流互感器通过在磁路中引入空气隙,大大增加了磁路阻抗,可有效避免铁心饱和对电流互感器性能的影响。从开口式电流互感器的基本磁路和电路时域方程出发,建立了考虑二次侧负载效应时表征开口式电流互感器工作性能的解析模型。讨论了开口式电流互感器的不同参数对其工作性能的影响。所建立的解析模型,对实现测量用电流互感器与保护用电流互感器的兼容,以及提高用于电能表在线检测的钳形电流互感器测量准确度,均具有理论指导价值。     

An analytical model for a TFET with an n-doped channel operating in accumulation and inversion modes

The tunnel field-effect transistor (TFET) is an ambipolar device that conducts current with the channel in both accumulation and inversion modes. Analytical expressions for the channel potential and current in a TFET with an n-doped channel when operating in the accumulation and inversion modes are proposed herein. The potential model is derived by solving the two-dimensional (2D) Poisson equation using the superposition principle while considering the charges present in the channel due to electron or hole accumulation along with the depletion charges. An expression for the tunneling current corresponding to the maximum tunneling probability is also derived. The tunneling current is obtained by analytically calculating the minimum tunneling length in a TFET when operating in the accumulation or inversion mode. The results of the proposed potential model is compared with technology computer-aided design (TCAD) simulations for TFET with various dimensions, revealing good agreement. The potential and current in an n-type TFET (nTFET) obtained using the proposed models are also analyzed.

     

基于复杂区域多层嵌入的三维模型隐写

本文以三维模型为隐写载体,提出一种基于结构复杂度的多层隐写方法.通过分析三维模型中各区域的结构复杂度,提取复杂度较高特征区域的顶点用于承载秘密数据.在这些顶点中,采用多层嵌入的隐写方法进行嵌入,只需修改模型中的少量数据就可实现高容量数据嵌入.该方法还可有效对抗面向三维模型的隐写分析方法,实验表明本文方法产生的含密三维模型很好地保持了二面角及面法向量的统计特性,使用基于一阶拉普拉斯平滑与特征统计的隐写分析方法难以进行隐写检测.     

An MR-compatible stereoscopic in-room 3D display for MR-guided interventions

Background and methods

A commercial three-dimensional (3D) monitor was modified for use inside the scanner room to provide stereoscopic real-time visualization during magnetic resonance (MR)-guided interventions, and tested in a catheter-tracking phantom experiment at 1.5 T. Brightness, uniformity, radio frequency (RF) emissions and MR image interferences were measured.

Results and discussion

Due to modifications, the center luminance of the 3D monitor was reduced by 14 %, and the addition of a Faraday shield further reduced the remaining luminance by 31 %. RF emissions could be effectively shielded; only a minor signal-to-noise ratio (SNR) decrease of 4.6 % was observed during imaging. During the tracking experiment, the 3D orientation of the catheter and vessel structures in the phantom could be visualized stereoscopically.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

An analytical approach for assessment of voltage sags

In this paper, analytical expressions for the calculation of remaining voltages due to fault at bus and along the line are derived. Balanced and unbalanced faults are considered and the effects of different fault distributions are taken into account. The proposed analytical methods are compared with the method of critical distance in order to achieve the acceptability of the proposed method. The developed method is applied to the IEEE 30-bus test system and a real Indian distribution system.     

An analytical approach for DG allocation in primary distribution network

This paper proposes an analytical expression to calculate the optimal size and an effective methodology to identify the corresponding optimum location for DG placement for minimizing the total power losses in primary distribution systems. The analytical expression and the methodology are based on the exact loss formula. The effect of size and location of DG with respect to loss in the network is also examined in detail. The proposed methodology was tested and validated in three distribution test systems with varying size and complexity. Results obtained from the proposed methodology are compared with that of the exhaustive load flows and loss sensitivity method. Results show that the loss sensitivity factor based approach may not lead to the best placement for loss reduction.     

Simulating spatial effects during condensation of steam in a model containment using the KUPOL-3D computer code

We present results from testing the KUPOL-3D computer code based on data obtained from an experiment on supercharging a model containment with steam that was carried out at the MISTRA test facility in accordance with the program of the ISP-47 international standard problem.     

An investigation of topology optimization for 3D magnetic shielding problems

Novel approaches to the 3D optimal design of magnetic shields are presented, in which topology optimization is achieved with the aid of numerical magnetic field analysis. The numerical procedures are implemented by means of a genetic algorithm combined with hybrid finite element and boundary element methods. This results in an overall increase in the optimization speed with acceptable computational accuracy. Finally, we present numerical results that demonstrate the validity of the proposed approach. © 1998 Scripta Technica. Electr Eng Jpn, 122(3): 55–61, 1998