Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $hbox{Dy}_{2}hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy₂O₃ cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy₂O₃ cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy₂O₃ cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.     

First Insight Into the Lifetime Acceleration Model of High-$k$ $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ Stacks for Advanced DRAM Technology Nodes

Long-term reliability results over six orders of magnitude in time are presented showing that the voltage acceleration model for $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ exhibits an exponential dependence with voltage, down to 2 V. The voltage acceleration parameter $gamma$ is between 10 and 15 $hbox{V}^{-1}$, depending on the biasing polarity. Soft-breakdown behavior (SILC) is evident prior to the onset of hard breakdown as a result of barrier lowering or charge accumulation in the high- $k$ film. Under ac stress conditions, this SILC branch is lowered in magnitude, translating to a gain in lifetime to breakdown.      

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Enhancement-Mode Buried-Channel $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As/In}_{0.52}hbox{Al}_{0.48}hbox{As}$ MOSFETs With High- $kappa$ Gate Dielectrics

The operation of long- and short-channel enhancement-mode In_0.7Ga_0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have V_t= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm²/Vldrs. For a gate length of 260 nm, the short-channel devices have V_t=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.     

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Numerical Study of Flicker Noise in p-Type $ hbox{Si}_{0.7}hbox{Ge}_{0.3}/hbox{Si}$ Heterostructure MOSFETs

Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si_0.7Ge_0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.     

Tunneling Effective Mass of Electrons in Lightly N-Doped $hbox{SiO}_{x} hbox{N}_{y}$ Gate Insulators

In this paper, we study the dependence of the tunneling effective mass of electrons on gate dielectric nitrogen concentration and thickness in MOSFETs with lightly doped silicon oxynitride $(hbox{SiO}_{x}hbox{N}_{y})$ gates. The direct tunneling current is modeled by applying a SchrÖdinger–Poisson solver with one-side-open boundary condition. The dependences of the effective mass on nitrogen concentration and dielectric thickness are extracted by fitting the computation results for the gate leakage current to the experimental data that we measured for samples with different thicknesses and nitrogen concentrations. Nitrogen concentration and thickness of samples are determined using X-ray photoemission spectroscopy. The obtained results show a strong dependence of the effective mass on the sample thicknesses and nitrogen concentration. The electron effective mass is found to increase as the thickness decreases, and the higher nitrogen concentration causes a reduction in effective mass.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

Structure Effects on Resistive Switching of $ hbox{Al/TiO}_{x}/hbox{Al}$ Devices for RRAM Applications

Resistive switching characteristics are investigated for Al/TiO_x/Al devices, particularly for the structural effects in crossbar and via-hole-type devices. The via-hole structure shows more reliable switching characteristics than the crossbar structure, owing to the elimination of possible edge effects. The asymmetric switching behavior is analyzed with top Al/TiO_x, and bottom Al/TiO_x interfaces. A trap-controlled space-charge- limited-current model is proposed as a possible switching mechanism, and it is verified that switching mainly occurs on the top electrode/TiO_x, interface side.     

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si_0.77Ge_0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm^-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.     

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

35-nm Zigzag T-Gate $hbox{In}_{0.52}hbox{Al}_{0.48} hbox{As/In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Metamorphic GaAs HEMTs With an Ultrahigh $f_{max}$ of 520 GHz

Metamorphic GaAs high electron mobility transistors (mHEMTs) with the highest-f _max reported to date are presented here. The 35-nm zigzag T-gate In_0.52Al_0.48As/In_0.53Ga_0.47As metamorphic GaAs HEMTs show f _maxof 520 GHz, f _T of 440 GHz, and maximum transconductance (g _m) of 1100 mS/mm at a drain current of 333 mA/mm. The combinations of f _max and f _T are the highest data yet reported for mHEMTs. These devices are promising candidates for aggressively scaled sub-35-nm T-gate mHEMTs.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

Schottky Barrier Height of Erbium Silicide on $ hbox{Si}_{1 - x}hbox{C}_{x}$

In this letter, the Schottky barrier height of erbium silicide contacts formed on $hbox{Si}_{1 - x}hbox{C}_{x}$ alloys was measured. The alloys were pseudomorphically grown on Si wafers with 0% to 1.2% C occupying the substitutional sites. Schottky barrier diodes were fabricated with an ideality factor of 1.13 or less. The hole barrier height was found to be 0.73 eV independent of the C concentration. This suggests that the electron barrier height should decrease with increasing C concentration due to the reduction in the semiconductor bandgap. For 1.2% C, the electron barrier is estimated to be 0.29 eV.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

Resistive Memory Switching of $hbox{Cu}_{x}hbox{O}$ Films for a Nonvolatile Memory Application

Poly crystalline Cu_xO films produced by plasma oxidation are investigated for nonvolatile memory applications. Reversible bistable resistive switching from a high-resistance state to a low-resistance state, and vice versa, is observed in an integrated Al/Cu_xO/Cu structure under voltage sweeping. More than 3000 repetitive cycles are observed in 180-mum memory devices with an on/off ratio of ten times. Data testing shows that the devices meet the ten-year retention requirement for the storage of programmed logic signals.