A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems

We present a 32 times 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mum times 56 mum , while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mum CMOS process.     

A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 m BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.     

A Simplified Calibration Methodology for On-Chip Couplers

In this paper, we propose a simplified calibration methodology for on-chip couplers to de-embed the unwanted but unavoidable parasitics introduced by the probing pads as well as the effects originating from redundant feeding lines. The traditional TRL (Thru, Reflect, Line) calibration technique for single-ended two-port device is extended and applied to symmetrical 4-port devices that can be decomposed as the odd- and even-mode equivalent circuits. Accordingly, the TRL calibration standards in the balanced format are designed as well. As a final step, single-ended 4-port S-parameters of device under test (DUT) are reconstructed through its de-embedded odd- and even-mode 2-port S-parameters. To validate the efficacy of our proposed calibration methodology in extracting S-parameters of DUT, models in HFSS, such as a branch-line coupler and a coupled-line coupler with probing pads, and balanced TRL calibration standards are generated. After performing the de-embedding procedures proposed in this paper, the extracted S-parameters agree well with the simulated S-parameters of DUT without adding any pads and feeding lines for measurement.     

Analysis and Design of a Wide-Tuning-Range VCO With Quadrature Outputs

A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed and implemented in the TSMC 0.18- $mu{rm m}$ CMOS process. The said QVCO uses a cross-coupled structure and a current-reuse technology to produce the quadrature signal and to save power consumption and area, respectively. Based on our measurement, the phase noise with 1-MHz offset from the carrier frequency of 3.6 GHz is $-$ 114 dBc/Hz and the proposed QVCO has a wide-band tuning range of 3.6–4.9 GHz. Also, the maximal phase error and power imbalance are less than 5$^{circ}$ and 1.5 dB, respectively, and the power consumption is 8 mW at 2-V power supply voltage.      

Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture

The design of a wide-tuning-range millimeter-wave CMOS VCO is presented in this paper. In contrast to the conventional wideband topologies, a nonuniform standing-wave oscillator utilizing tapered gain elements, switched transmission lines and distributed varactors is employed to provide an extended output range with the coarse and fine frequency tuning. Due to the use of the transmission line architecture and the position-dependent amplitude of the standing waves, the loading effects of the varactors and the MOS switches can be alleviated, enabling the VCO to operate at higher frequencies. Using a 0.18-mum CMOS process, a 40-GHz VCO is designed and implemented. Consuming a DC power of 27 mW from a 1.5-V supply voltage, the fabricated circuit exhibits a frequency tuning range of 7.5 GHz with an output power level ranging from -13.6 to -4 dBm. The measured phase noise at 1-MHz offset is lower than -96 dBc/Hz within the entire frequency range. This work demonstrates the widest tuning range in percentage among the CMOS VCOs at millimeter-wave frequencies.     

A 2.45-GHz Near-Field RFID System With Passive On-Chip Antenna Tags

The design of a 2.45-GHz near-field RF identification (RFID) system with passive on-chip antenna (OCA) tags is very challenging as the efficiency of RF power conversion is very low. It poses multidisciplinary research challenges such as ultra-low-power circuits design, semiconductor process technology, and integrated antenna design. This paper describes the designs of such an RFID system, the reader, and OCAs, as well as the passive tag integrated circuits in detail. The passive tag chip with 128-bit nonvolatile memory has been realized using CMOS 0.13- technology. The OCA is fabricated on top of the chip using post-processing technology. The complete RFID tag with an integrated OCA is smaller than 0.5- with a thickness of 0.1 mm. With the reader generating an output power of 0.5 W, the RFID system is able to perform with RF read/write functions at a distance of .     

一种瞬态响应增强的片上LDO系统设计

分析了传统LDO提高系统稳定性及瞬态响应的局限性,提出了一种片内集成补偿技术。该技术无需外挂电容和等效串联电阻(ESR),即可使系统在全负载范围内保持稳定,并具有良好的纹波抑制能力。仿真结果表明,系统空载时静态电流为46μA,且能提供200mA的最大负载电流,低频电源抑制比达到-65.6dB,启动时间只有16μs,在输出电容为10pF、负载电流以200mA/2μs突变时,最大下冲电压为120mV,上冲电压为160mV。     

大电流负载的片上LDO系统设计

 本文分析了传统大电流负载的LDO(Low-dropout Regulator)系统实现系统稳定性和瞬态响应提高的局限性,在此基础上,提出了一种片内集成的瞬态响应提高技术.此技术无需外挂电容和等效串联电阻(Equivalent Series Resistor,ESR),即能使系统在全负载范围内保持稳定性和良好的纹波抑制能力.仿真结果表明,系统空载时,静态电流为64μA,且最大能提供800mA的负载电流,1KHz时的电源抑制比达到-60dB,当负载电流以800mA/5μs跳变时,最大下冲电压为400mV,上冲电压为536mV,恢复时间分别只需6.7μs和12.8μs,版图面积约为0.64mm².     

一种基于JTAG的SoC片上调试系统的设计

基于SoC的硬件设计,提出了一种基于JTAG的SoC3片上调试系统的设计方法.该调试系统可设置多种工作模式,含有CPU核扫描链和片上总线扫描链.能硬件实现调试启动与停止、断点设置、单步执行及存储访问等调试功能.对外围IP模块调试诊断时,可绕开CPU核,通过片上总线扫描链直接进行读写访问.该调试系统对其他SoC的设计具有一定的参考价值.     

On-Chip Liquid Cooling With Integrated Pump Technology

In this paper, the capability of a novel cooling system for microchannels based on the principle of electrowetting is examined. To start with, the elcctrowetting effect in microchannels is experimentally investigated. The used electrowetting system consists of a liquid droplet deposited on a conductive Si substrate and electrically insulated from this substrate by a dielectric, layer. Microchannels of 100 mum times 100 mum are etched in the substrate. By applying an ac voltage signal between the droplet and the substrate, the microchannels can be periodically tilled and emptied with the liquid of the droplet. This oscillating liquid flow will be used to cool the chip. For the 100 mum times 100 mum microchannels a voltage of 51 V is required for the actuation. Further, based upon the results of the filling of the channels the cooling capacity of the proposed system is theoretically investigated. The theoretically achievable cooling rate of this enhanced system is compared to the heat transfer by conduction through a silicon substrate. A critical filing period is found; for shorter filling periods, the heat transfer will be improved by inserting microchannels, for higher filling periods the electrowetting deteriorates the cooling. It can be concluded that the proposed system is promising, especially when frequencies in the range of a few Hz can be achieved.     

一种带温度和工艺补偿的片上时钟振荡器

基于SMIC0.18gm 1P6M的标准CMOS工艺,设计并实现了一种带温度补偿和工艺偏差校准的60MHz片上CMOS时钟振荡器.经仿真和流片测试验证,该结构的时钟振荡器输出频率能很好的稳定在60-61MHz,温度从-25℃变化至75℃时,频率仅变化108.5kHz,在对时钟精度要求不高的应用下,完全可以取代片外的石英晶振,降低成本.     

一种新颖的低功耗低相位噪声VCO设计

作为收发器的重要模块,与其他收发器模块相比,压控振荡器(VCO)消耗了大量能源。由于许多射频应用系统采用电池作为能源,如WiFi、蓝牙及物联网等系统,因此,在保持合理的系统性能的前提下,需尽量降低功耗。该文研究了标准VCO结构的性能,并提出了一种新的CMOS VCO电路结构。与传统的CMOS VCO相比,该文提出的CMOS VCO只需较少的外部偏置电流便可产生更高的跨导,因而可以消耗更低的功耗。在1.8 V电压供电下,该文提出的VCO仅消耗了2.9 mW,取得了-124.3 dBc/Hz@1 MHz的相位噪声。     

低相位噪声压控振荡器设计

分析了LC压控振荡器(VCO)相位噪声,通过改进电路结构,采用PMOS和NMOS管做负阻管,在尾电流源处加入电感电容滤波,优化电感设计,设计了一种高性能压控振荡器.采用TSMC 0.18 μm IP6M CMOS RF工艺,利用Cadence中的Spectre RF工具对电路进行仿真.在电路的偏置电流为6 mA、电源电压VDD=1.8 V时,输入控制电压为0.8～1.8 V,输出频率变化为1.29～1.51 GHz,调谐范围为12.9%,相位噪声为-134.4 dBc/Hz@1MHz,功耗仅为10.8 mW.     

推-推压控振荡器的仿真设计

在对构成推-推振荡器的基本振荡单元进行常规奇偶模分析的基础上,采用添加辅助信号源的方法,对合成后的频率调谐特性、输出功率及基波抑制特性进行了仿真模拟。并利用负载牵引法对二次谐波匹配网络进行了优化。根据仿真结果设计的X波段推-推压控振荡器,采用封装硅晶体管及砷化镓变容管,在1GHz调谐带宽内,输出功率2～8dBm。     

面向可重用SoC设计的片上总线

引言随着深亚微米技术的发展和应用,工艺上已经允许设计包含几亿个晶体管的芯片。运用这种工艺,完全可以实现在一块芯片内集成一个系统,即所谓的SoC,这样必然使芯片的设计方法也随之发生变化。复杂芯片的设计中最常用的方法是可重用设计。目前,设计人员面临的挑战已经不再是是否有必要采用可重用设计方法,而是如何使用可重用设计方法,从而使它在设计过程中发挥更高的效率。可重用设计的总线标准如何在实际设计时更有效地对各种IP核进行互联是可重用设计方法关注的一个重要问题。如果在设计中采用自定义总线,可能会得到比较优化的性能,但是…     

Efficient On-Chip Crosstalk Avoidance CODEC Design

Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of datawords to codewords has been proposed for CODEC design. This is mainly due to the nonlinear nature of the crosstalk avoidance codes (CAC). The lack of practical CODEC construction schemes has hampered the use of such codes in practical designs. This work presents guidelines for the CODEC design of the “forbidden pattern free crosstalk avoidance code” (FPF-CAC). We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists based on the representation of numbers in the Fibonacci numeral system. Our first proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed.      

Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique

In this paper, an integrated adaptive-output switching converter is proposed. The design employs a one-cycle control for fast line regulation and a single outer loop for tight load regulation and fine tuning. A switched-capacitor integrator is introduced to the one-cycle control to obtain positive integration with a single positive power supply, allowing a standard low-cost CMOS fabrication process. To improve the efficiency, a dynamic loss control technique is presented. The converter was designed and fabricated with 0.35 $mu{hbox{m}}$ N-well CMOS process. With a supply voltage of 3 V, a voltage ripple of less than $pm$20 mV is measured. The maximum efficiency is 92% with a load power of 475 mW. The converter exhibits a tracking speed of 23.75 $mu{hbox{s/V}}$ for both start-up and reference voltage transitions. The recovery time for a 20% load change is approximately 9.5 $mu{hbox{s}}$.      

全自动引线键合机校正系统设计与实现

简要阐述了键合机中校正系统设计,包括伺服系统校正,图像系统校正,物料系统校正等。     

CMOS Quadrature VCO Implemented With Two First-Harmonic Injection-Locked Oscillators

This letter presents a new quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two first-harmonic injection-locked oscillators (ILOs). The outputs of one ILO are injected to the gates of the tail transistors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.582 times 0.972 mm². At the supply voltage of 1.0 V, the total power consumption is 8.0 mW. The free-running frequency of the QVCO is tunable from 5.31 GHz to 5.75 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz offset is -120.01 dBc/Hz at the oscillation frequency of 5.31 GHz and the figure of merit (FOM) of the proposed QVCO is about -185.48 dBc/Hz.     

高线性度VCO的研制

本文描述了一种高线性度VCO的电路设计和实验结果。该器件线性度优于0，8％，且不需要采用外围线性度校正电路，具有调试简单、体积小、成本低、可靠性高的特点。