80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor f_T/f_MAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P _1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP ₃ of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm² and 0.35times0.40 mm², respectively     

10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-mum CMOS technology is demonstrated. The high-frequency quadrature RF and LO₁ signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO₂ quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP_{1 dB} of -16 dBm, IIP₃ of -5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.     

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P_{1 dB} and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P_{1 dB}, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio     

A 3.3 mW K-Band 0.18-μ m 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair

This letter presents a low-power active bandpass filter (BPF) at K-band fabricated by the standard 0.18 mum 1P6M CMOS technology. The proposed filter is evolved from the conventional half-wavelength resonator filter, using the complementary-conducting-strip transmission line (CCS TL) as the half-wavelength resonator. Furthermore, the complementary MOS cross-couple pair is proposed as a form of current-reuse scheme for achieving low-power consumption and high Q-factor simultaneously. The simulated results indicate that the Q-factor of the proposed half-wavelength resonator can be boosted from 9 to 513 at 25.65 GHz compared with the resonator enhanced by the nMOS cross-couple pair to Q-factor of merely 43 under the same power consumption. The proposed active BPF of order two occupies the chip area of 360 mum times 360 mum without contact pads. The measured results show that the center frequency of the active BPF is 22.70 GHz and a bandwidth of 1.68 GHz (7.39 %). The measured P_{1 dB} and noise figure at 22.70 GHz are -7.65 dBm and 14.05 dB, respectively. There is a 56.84 dB suppression between the fundamental tone and the second harmonic when the input power is -11.26 dBm. While showing 0 dB loss and some residual gain, the active BPF consumes 2.0 mA at 1.65 V supply voltage with maximum of 0.15 dB insertion loss and 9.96 dB return loss at pass band.     

A High Gain 77 GHz Power Amplifier Operating at 0.7 V Based on 90 nm CMOS Technology

A 77 GHz 90 nm CMOS power amplifier (PA) demonstrates a gain of 17.4 dB and a saturated output power of 5.8 dBm at a low supply voltage of 0.7 V. To take care of hot-carrier injection degradation, the supply voltage is reduced from a standard voltage of 1.0 V. The saturated output power is increased to 9.4 dBm with a linear gain of 20.6 dB at 1.0 V operation. The amplifier consists of three-stage common-source nMOSFETs with gate widths of 40, 80, and 160 $mu{rm m}$. To our best knowledge, the developed PA shows the highest gain ever achieved for W-band CMOS amplifier. The measured temperature characteristics suggest that a simple compensation technique is possible by gate bias control.      

基于InGaP/GaAs HBT的X波段MMIC功率放大器研制

研制了X波段的InGaP/GaAs HBT单级MMIC功率放大器,该电路采用自行开发的GaAs HBT自对准工艺技术制作.电路偏置于AB类,小信号S参数测试在8～8.5GHz范围内,线性增益为8～9dB,输入驻波比小于2,输出驻波比小于3,优化集电极偏置后,线性增益为9～10dB.在8.5GHz进行连续波功率测试,在优化的负载阻抗条件下,P1dB输出功率为29.4dBm,相应增益7.2dB,相应PAE〉40%,电路的饱和输出功率Psat为30dBm.     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

60 G Hz 11 dBm CMOS功率放大器设计

近年来60 GHz附近的一个连续频段可以自由使用,这为短距离的无线个域网等高速率传输的应用提供了条件.设计了一个工作在60 GHz的CMOS功率放大器.采用台积电0.13μmRF-CMOS工艺设计制造,芯片面积为0.35mm × 0.4 mm,最大线性输出功率为11 dBm,增益为9.7 dB,漏极增加效率(η_(PAE))为9.1%.达到应用在通信距离为10 m的无线个域网(WPAN)射频电路中的要求.设计中采用了厚栅氧化层工艺器件和Load-Pull方法设计最优化输出阻抗z_(opt),以提高输出功率.该方法能较大提高CMOS功率放大器的输出功率,可以应用到各种CMOS功率放大器设计中.     

1.2V and 8.6mW CMOS differential receiver front-end with 24 dB gain and -11dBm IRCP

A 60 GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24 dB without buffer amplifier), high linearity (-11 dBm input referred P_{1 dB} compression point, or IRCP), low power dissipation (4.3 mW/arm) and small die area (0.022 mm²)     

An Integrated Wideband Power Amplifier for Cognitive Radio

This paper presents the development of the wideband power amplifier (PA) for application to intelligent cognitive radios. The load-tracking based on the frequency-varied load-pull technique is proposed for the PA design. The load impedance tracking is realized by filter network synthesis. A 3-7.5-GHz broadband PA is demonstrated in 0.15-mum InGaAs pseudomorphic HEMT technology. Operated at 3.5 V, the P_{1 dB} and power-added efficiency of the PA are better than 21.4 dBm and 20%, respectively.     

A Ku-Band Interference-Rejection CMOS Low-Noise Amplifier Using Current-Reused Stacked Common-Gate Topology

A Ku-band CMOS low-noise amplifier (LNA) with high interference-rejection (IR), wide gain control range, and low dc power consumption is presented. The LNA consists of two common-gate metal-oxide-semiconductor field-effect transistors interconnected with an interstage parallel tank for the IR. The stacked common-gate stages share the same dc bias current to reduce power consumption and have controllable gain by changing this dc current. The implemented 0.13 mum CMOS LNA achieves measured power gain of 10.8 dB, noise figure of 4.2 dB, output P₁ dB of -4.3 dBm at 15 GHz, while rejecting interference down to a 38.5 dB level. The gain control range is 23.3 dB by varying the gate voltage from 0.2 to 1.2 V. The LNA consumes only 4 mA from a 1.3-V supply.     

多晶发射极双台面微波功率SiGe HBT

研制成功了可商业化的75mm单片超高真空化学气相淀积锗硅外延设备SGE500,并生长了器件级SiGe HBT材料.研制了具有优良小电流特性的多晶发射极双台面微波功率SiGe HBT器件,其性能为:β=60@VCE/IC=9V/300μA,β=100@5V/50mA,BVCBO=22V,ft/fmax=5.4GHz/7.7GHz@10指,3V/10mA.多晶发射极可进一步提供直流和射频性能的折衷,该工艺总共只有6步光刻,与CMOS工艺兼容且(因多晶发射极)无需发射极外延层的生长,这些优点使其适合于商业化生产.利用60指和120指的SiGe HBT制作了微波锗硅功率放大器.60指功放在900MHz和3.5V/0.2A偏置时在1dB压缩点给出P1dB/Gp/PAE＝22dBm/11dB/26.1%.120指功放900MHz工作时给出了Pout/Gp/PAE＝33.3dBm (2.1W)/10.3dB/33.9%@11V/0.52A.     

A W-Band Medium Power Amplifier in 90 nm CMOS

A W-band CMOS medium power amplifier (PA) is presented in this letter. The circuit is implemented in 90 nm mixed signal/radio frequency CMOS process. By utilizing balanced architecture, the PA demonstrated a measured maximum small signal gain of 17 dB with 3 dB bandwidth from 91 to 108 GHz. The saturation output power $(P_{rm sat})$ is 12 dBm between 90 and 100 GHz for $V_{rm ds}$ of each transistor at 1.5 V. To our knowledge, this is the highest frequency CMOS PA to date.      

A 60 GHz SiGe-HBT Power Amplifier With 20% PAE at 15 dBm Output Power

A monolithic power amplifier (PA) operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 SiGe-heterojunction bipolar transistor (HBT) technology, featuring npn transistors with and . A two-stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a small signal gain of 18.8 dB and an output power of 14.5 dBm under 1 dB gain compression at 61 GHz. At this frequency, the saturated output power is 15.5 dBm and the peak power added efficiency (PAE) is 19.7%. To our knowledge, this is the highest PAE reported so far for a monolithic 61 GHz PA in SiGe-HBT technology.     

A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.     

A Cool, Sub-0.2 dB Noise Figure GaN HEMT Power Amplifier With 2-Watt Output Power

This paper reports on a S-, C-band low-noise power amplifier (LNPA) which achieves a sub-0.2 dB noise figure (NF) over a multi-octave band and a saturated output power (Psat) of 2 W at a cool temperature of -30degC . The GaN MMIC is based on a 0.2 mum AlGaN/GaN-SiC HEMT technology with an f_T ~ 75 GHz. At a cool temperature of -30degC and a power bias of 15 V-400 mA, the MMIC achieves 0.25-0.45 dB average NF over a 2-8 GHz band and a linear P_1dB of 32.8 dBm ( ~ 2 W) with 25% power-added efficiency (PAE). At a medium bias of 12 V-200 mA, the amplifier achieves 0.1-0.2 dB average NF across the same band and a P_1dB of 32.2 dBm (1.66 W) with 35% PAE. The corresponding saturated output power is greater than 2 W. At a low noise bias of 5 V-200 mA, a remarkable 0.05-0.15 dB average NF is achieved with a P_1dB > 24 dBm and PAE ~ 33%. These results are believed to be the lowest NF ever reported for a multi-octave fully matched MMIC amplifier capable of > 2 W of output power.     

Watt-level Ka- and Q-band MMIC power amplifiers operating at lowvoltages

Ka- and Q-band watt-level monolithic power amplifiers (PAs) operating at a low drain bias of 3.6 V are presented in this paper. Design considerations for low-voltage operation have been carefully studied, with an emphasis on the effect of device models. The deficiency of conventional table-based models for low-voltage operation is identified. A new nonlinear device model, which combines the advantages of conventional analytical models and table-based models, has been developed to circumvent the numerical problems and, thus, to predict optimum load impedance accurately. The model was verified with load-pull measurements at 39 GHz. To implement a low-voltage 1-W monolithic-microwave integrated-circuit amplifier, careful circuit design has been performed using this model. A Q-band two-stage amplifier showed 1-W output power with a high power gain of 15 dB at 3.6-V drain bias. The peak power-added efficiency (PAE) was 28.5% and 1-dB compression power (P_{1 dB}) was 29.7 dBm. A Ka-band two-stage amplifier showed a P_{1 dB} of 30 dBm with 24.5-dB associated gain and 32.5% PAE. Under very low dc power conditions (P_dc<2 W, V_ds=3.4 V), the amplifiers showed 29-dBm output power and PAE close to 36%, demonstrating ultimate low-power operation capability. To the best of our knowledge, this is the first demonstration of watt-level PA's under 3.6-V operation at 26 and 40 GHz. Compared with the published data, this work also represents state-of-the-art performance in terms of power gain, efficiency, and chip size     

Ku波段10W功率PHEMT

报告了研制的 9.6mm栅宽双δ-掺杂功率 PHEMT,在 fo=1 1 .2 GHz、Vds=8.5 V时该器件输出功率3 7.2 8d Bm,功率增益 9.5 d B,功率附加效率 44.7% ,在 Vds=5～ 9V的范围内 ,该器件的功率附加效率均大于42 % ,两芯片合成 ,在 1 0 .5～ 1 1 .3 GHz范围内 ,输出功率大于 3 9.92 d Bm,最大功率达到 40 .3 7d Bm,功率增益大于 9.9d B,典型的功率附加效率 40 %。