高效能耗传感器网络的模型分析与路由算法设计

传统的传感器网络生命期模型未考虑节点异跳上单位传输费用的差异性,针对该缺点本文建立生命期模型并转化目标为带不等式约束的最大费用最大流问题,依据模型中所体现路由规划与生命期优化的本质联系,提出一种基于节点负载压力的自适应路由算法,算法实现所需的计算量、通信量较小.通过仿真实验对算法进行了性能分析和验证,仿真结果表明该算法能有效地延长传感器网络生命期.     

CALYPSO — Critical Area, Lifetime, and Yield Predicting Software

This contribution is divided into three parts. First we introduce a new procedure for the extraction of defect size distributions taken into account the real defect outline. In the second part a definition for reliability metal defects is given. Based on this definition a new lifetime prediction model for metal lines is introduced and theoretical and experimental results are compared. Our new yield and lifetime predicting software system CALYPSO is represented in the third part of the paper. The highlights of CALYPSO are the very high speed of the calculations, the implementation of the above mentioned lifetime prediction algorithms, and a module for the build-in reliability check of layout data.     

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

超平面布线

本文大胆打破了传统通道模型的束缚,建立了一个能更好体现多层布线内在本质约束的新模型：超平面布图模型,在该模型下提出了超平面布线算法。该算法以全新的逆向删冗策略成功地解决了布线线序的问题,使线网布线真正达到了并行处理。算法遵循了王守觉先生关于总体分析的方法作为解决超平面布线问题的指导思想,以布线层数最少化和通孔最少化为目标,通过动态地分析线网间的相互位置关系,全局考虑去释放各线网占据的不合理布线资源     

真实缺陷的矩形模型及其关键面积计算

在集成电路(IC)中,为了进行有效的成品率估计和故障分析,与光刻有关的缺陷形状通常假设为圆模型.然而,真实缺陷的形状多种多样.本文提出一种真实缺陷的矩形模型及与之相关的关键面积计算模型,该模型既考虑了真实缺陷的形状又考虑了IC版图布线的特点.在缺陷引起故障概率预测方面,仿真结果表明新模型比圆模型更接近真实缺陷引起的故障概率.     

矩形缺陷轮廓的成品率模型

现有成品率及关键面积估计模型中,假定缺陷轮廓为圆,而实际缺陷轮廓为非规则形状.本文提出了矩形缺陷轮廓的成品率模型,该模型与圆模型相比,考虑了缺陷的二维分布特性,接近真实缺陷形状及IC版图布线和成品率估计的特点.比较了新模型与真实缺陷及其圆模型引起的成品率损失,表明新模型在成品率估计方面更加精确,这对成品率精确估计与提高有重要意义.     

Yield Modeling of Rectangular Defect Outline

In integrated circuits,the defects associated with photolithography are assumed to be in the shape of circular discs in order to perform the estimation of yield and fault analysis.However,real defects exhibit a great variety of shapes.In this paper,a novel yield model is presented and the critical area model of short circuit is correspondingly provided.In comparison with the circular model corrently available,the new model takes the similarity shape to an original defect,the two-dimensional distributional characteristic of defects,the feature of a layout routing and the character of yield estimation into account.As for the aspect of prediction of yield,the experimental results show that the new model may predict the yield caused by real defects more accurately than the circular model does.It is significant that the yield is accurately estimated and improved using the proposed model.     

基于双层递归神经网络模型求解最优组播路由

基于覆盖网络的组播作为一种新的IP网络组播解决方案已得到广泛关注。提出了一种利用改进的双层递归神经网络模型求解VPON网络环境下的QoS（服务质量）最优组播路由的方案。该方案在选择路由时综合考虑链路的可用带宽及节点的剩余处理能力，并运用一种基于改进的双层递归神经网络模型——MTLRNN进行求解，与其它启发式组播路由算法相比，该方案在满足应用的QoS要求的前提下，使全网的负载分配更加均衡，同时在解的有效性及接纳的组播应用会话数方面都有比较大的改善。     

一种基于拉格朗日松弛法的QoS路由算法

本文提出了一个新的QoS路由算法,可以有效地求解延时约束条件下的最小代价问题。算法以拉格朗日松弛法为基础,将链路代价参数吸收到延时参数中,同时在迭代过程中结合延时约束条件,可以在多项式时间内找到一个较优解,并对该算法进行了分析和仿真,结果表明该算法比其它一些同类算法在性能上有较大的改善。     

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO₂ as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO₂ as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO₂ is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO₂ devices. A cell layout is provided and the DRAM circuit characteristics are also presented.     

Routing Algorithms in WDM Networks under Mixed Static and Dynamic Lambda-Traffic

Dynamic traffic is becoming important in WDM networks. In the transition towards full dynamic traffic, WDM networks optimized for a specific set of static connections will most likely also be used to support on-demand lightpath provisioning. Our paper investigates the issue of routing of dynamic connections in WDM networks which are also loaded with high-priority protected static connections. By discrete-event simulation we compare various routing strategies in terms of blocking probability and we propose a new heuristic algorithm based on an occupancy cost function which takes several possible causes of blocking into account. The behavior of this algorithm is tested in well-known case-study mesh networks, with and without wavelength conversion. Moreover, Poissonian and non-Poissonian dynamic traffics are considered.     

Circuit layout

This paper gives a general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits. A lot of attention is given to the layout of large and complicated circuits, in particular, to the layout of very-large-scale-integration (VLSI) chips. Though the paper is an overview, and one could almost say a tutorial, it is intended for readers with some basic knowledge of what a circuit layout is and what some of the basic problems are. The main subjects discussed are: assignment of gates, placement methods, loose routing, final routing, and problems associated with the implementation of a hierarchical system. The emphasis is on new, not widely published methods, and on methods that seem to have potential for solving some of the current problems. Practical examples illustrate this rather personal account of circuit layout and sugsest where we may go from here.     

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.     

具有单元自动生成的多元胞布图方法

本文提出一种新的多元胞自动布图方法.主要由四个部分构成,块的生成、块内一维布局、单元生成、通道布线.其中第一部分采用了分析的方法完成各个块的生成,目标为使连线最短和块之间连线和隔块连线最少.第二部分中引入了伪单元的概念以处理含有约束的一维布局问题,解决了各个块之间的相互连线关系以及隔块连线.第三部分中的单元生成,引入了类似硅编译的一些思想,在硅编译与传统的自动布局方法之间的结合方面做一些有益的尝试.第四部分的通道布线是一个比较灵活的方法,可以解决用户提出的各种工艺上的要求的布线,提高了布图的物理性能. 整个过程用C语言编成程序并已在PCS-68000机上运行.     

Board-level multiterminal net assignment for the partial cross-bar architecture

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.     

Dynamic network evolution, with examples from AT&T's evolvingdynamic network

Dynamic network evolution achieves network performance improvement and cost reduction by taking advantage of new advanced technologies being introduced into the network to achieve greater network flexibility and efficiency. The author describes the evolution of dynamic networks, with examples drawn from the AT&T DNHR network deployed in the '80s and RTNR network deployed in the '90s. Dynamic traffic routing implements an integrated class-of-service routing feature for extending dynamic routing to emerging services, and provides a self-healing network capability to ensure a network-wide path selection and immediate adaptation to failure. Dynamic traffic routing brings benefits to customers in terms of new service flexibility and improved service quality and reliability, at reduced cost     

The Integrated Room Layout for a Semiconductor Facility Plan

Layout study is important because layout largely determines the initial investment and production efficiency of a plant as compared with other downstream activities. Especially for semiconductor production, the continued miniaturization of chips requires increased investment and operating cost. While approximately one billion U.S. dollars was necessary for a new semiconductor fab in 1995, manufacturers today need to invest two to three times that for the same type of facility. This research presents a new integrated room layout for a semiconductor fab. Machine tools are laid out in four large rooms. The tools in each room are connected by one overhead hoist transporter/overhead shuttle loop. This layout increases direct inter bay transportation, product mix change flexibility, and routing flexibility and reduces transportation time and initial investment cost. The performance of this new layout is compared with the integrated bay layout that is favorably considered and being used in the literature and industry. This comparison uses data provided by International SEMATECH.     

基于图像处理的版图优化方法

随着集成电路技术进入深亚微米技术节点,提高成品率成为研究热点问题。文中提出了一种基于图像处理的版图优化方法来提高成品率。该方法首先确定两个待优化线网和其可移动空间,再找出两个待优化线网的最佳移动位置,将两个待优化线网移动后所减小短路关键面积最大的线网,作为本次优化的线网,实现对版图的优化。文中提出的优化方法不但考虑了缺陷的真实轮廓特征和粒径分布特征,而且不受版图线网的形状的制约,为版图优化提供了更准确的依据。