聚酰亚胺表面化学沉铜前处理的微观分析

讨论了聚酰亚胺(PI)沉铜前处理过程对孔内沉铜空洞的可能影响,利用扫描电子显微镜分析了每道前处理后PI的微观表面状态。实验表明,只有当PI表面被PI调整剂粗化后方可以提高沉铜层与PI之间的结合力,而且沉铜层与PI间的结合力还与沉铜时间相关。     

一种应用于全印制电子沉铜催化浆料制备及其应用

制备出一种应用于全印制电子沉铜催化浆料,采用电化学工作站的开路电位-时间(OCP-t)的技术,测定活化浆料引发沉铜的Emix-t曲线,比较不同含银量对引发过程的影响;在此基础上,应用于制造电子标签(RFID)。结果表明:随银含量增大,缓慢生成铜活性中心的诱导时间越短,活性越高;沉铜催化浆料及其对应的工艺加成法制作的电子标签导电性和结合力符合工业化要求,可以作为一种全印制电子技术来推广应用。     

低应力化学沉铜浅析

文章简述了低应力化学沉铜的工艺特点,通过简单的对比实验分析了其与传统化学沉铜的不同,以期加深读者对低应力化学沉铜工艺的理解。     

水平沉铜树脂塞孔板盖帽不良影响因素研究

树脂塞孔板通过沉铜板电等流程制作,将塞孔位置镀上一层铜,用于满足PCB后续产品的焊接,当沉铜不良,则会导致后续树脂上无法镀上所需的铜,影响PCB焊接,而影响沉铜不良的因素主要有化铜活性、活化Pd不良、沉铜药水与树脂不匹配等因素,文章主要通过实验和过程确认,验证树脂塞孔沉铜不良的品质影响因素,为能更好地解决因盖帽不良造成的报废,现从多个角度分析影响树脂塞孔盖帽不良的因素,找出最佳生产参数,有效地实现了树脂塞孔盖帽不良问题的改善。     

以DOE实验方法来研究非甲醛沉铜技术

本文介绍了如何用DOE的实验方法来研究非甲醛沉铜技术，并使用Minitab来详细分析其结果，最终得到影响非甲醛沉铜技术的关键因素。     

电镀铜粉产生原因分析及验证

电镀铜粉严重影响电路板的品质,其偶发性非常难以监测。而铜粉的产生对产品的可靠性有着致命的影响,其形成过程也曾困扰了很多优秀的工程师。本文从沉铜和电镀流程中铜粉产生的过程进行分析,论述了从沉铜到全板电镀加工过程中铜粉产生的几种原因,并通过实验验证了铜粉产生的原因。     

化学沉铜工艺中背光失效分析及改善探讨

主要讲述化学沉铜工艺中背光失效问题,通过对一次沉铜背光不良原因的查找及分析,并给出相应的改善措施,达到有效改善此类异常引发的沉铜背光失效的目的。     

高Tg多层印制板孔壁微裂纹的改善

在印制板的化学沉铜过程中,用于中Tg基板的工艺流程和配方,在加工高Tg基板时会出现非钻孔腻污等常见现象引起的孔壁微裂纹。实验表明,在不改变溶液体系的情况下,通过改善化学沉铜工艺流程和优化配方两种方法,可以极大的改善高他印制板的孔壁微裂纹情况,其中化学沉铜槽的配方对孔壁微裂纹起到决定性的影响。     

超高导热金刚石铜复合材料在GaN器件中的应用

金刚石铜具有高导热率和低膨胀系数,可用于大功率芯片的散热热沉.未做处理的金刚石表面非常光滑,不易附着其他金属,由于金刚石性质非常稳定,不容易被强酸和强碱进行表面处理.采用JG-01金刚石铜粗化处理液对金刚石进行粗化处理,而对铜无损伤,提升了金刚石表面结合力.金刚石铜镀层对金锡(AuSn)和锡铅(PbSn)焊料的润湿性满足GJB548B-2005要求.GaN功率放大器芯片采用金刚石铜热沉比铜钼铜热沉结温可以降低12℃.金刚石铜载板镀层润湿性良好,焊接后芯片底部的空洞率不大于3％,热沉焊接后空洞率不大于5％,满足高功率芯片散热要求.按照产品环境适应要求,对GaN功率放大器做了高低温冲击和机械振动两种环境筛选实验,最终满足可靠性考核要求.     

人造金刚石热沉的锁相列阵半导体激光器热特性计算分析

用镜象法求解金刚石薄膜和铜组成的热沉中的热传导方程,计算了不同厚度金刚石薄膜对器件温升和各条间温差的影响。     

Selective deposition of a thin copper film for metallization on silicon by the chemical bath process

Recently copper as metallization for contact and interconnect in VLSI is attracting attention. In this study, copper has been selectively deposited over defined areas on glass and silicon using the chemical bath deposition technique. A continuous copper film with a resistivity of 1.87 μΩ cm for 6000 Å thickness is formed. The rate of deposition and the film resistivity are studied. The deposition process and its characteristics are discussed.     

Two‐Dimensionally Ordered Copper Grid Patterns Prepared via Electroless Deposition Using a Colloidal‐Crystal Film as the Template

Two‐dimensionally ordered copper grid patterns with different pore sizes and thickness have been fabricated via electroless copper deposition using a colloidal‐crystal film as the template. The pore size of the grid can be adjusted by altering the deposition time. The copper films, with thicknesses of ≈ 100–130 nm and pore sizes of ≈ 100 nm, are flexible and can be peeled off a silicon wafer and rolled up into a reel. Three‐dimensionally ordered porous copper materials have also been prepared using a similar method.     

Stress development during evaporation of Cu and Ag on silicon

This work presents results of stress measurements during deposition of thin silver and copper films on 100 μm Si substrate. The stress in thin films has been determined by means of an optical system for the measurement of sample’s curvature. This system was applied in situ in a high vacuum deposition system. For Ag films the stress occurring during deposition goes from a low compressive value to tensile for thickness less than 30 nm and to compressive above this. For Cu films we observe tensile stress for thickness less 20 nm and above 50 nm. The same general trend of stress evolution with thickness is present in all cases at initial stage. There is the same growth mode for Cu and Ag because of the similar shapes of stress curves for thickness lower than 30 nm The behavior of stress evolution was explained by island nucleation and growth, island coalescence and continuous film growth. The difference in the stress evolution above 30 nm is caused by the fact that silver may be less sensitive than copper to adsorption of impurities. Adsorbed contamination inhibits compressive stress increase generated by grain boundary and defects remaining in the film.     

Barrier layers for Cu ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.     

Room temperature electroless plating copper seed layer process for damascene interlevel metal structures

Described in this paper is the development of a room temperature electroless copper seed layer deposition process on ultra-thin TiN barrier layers. This novel process is compatible with damascene interlevel metal structures for sub-0.18 micron ULSI processes. An optimum copper layer thickness of 50 nm and a deposition rate of 45 nm min⁻¹ was targeted and obtained. Atomic force microscopy (AFM) reveals that the non-uniformity of the seed layer is less than 10% of the film thickness, while four-point probe measurements indicate that the resistivity of the copper seed layer is less than 6 μΩ cm⁻¹. Secondary ion mass spectroscopy (SIMS) reveals that potential metallic contaminants such as sodium, potassium, calcium and magnesium ions do not penetrate the TiN barrier layer. Rutherford back scattering (RBS) indicates that the palladium concentration in the seed layer is approximately 1%, which is low enough to avoid wafer contamination and increased resistivity in the subsequent electroplated copper layer.     

Characterization of copper grain growth limitations inside narrow wires depending of overburden thickness

With the downscaling of feature dimensions, copper interconnects exhibit properties differing from bulk or film material. Resistivity increases and limits electrical performances, and reliability of interconnects becomes a more important challenge for each new technological node. In this study, we present an approach of copper grain growth control inside narrow wires by adding a step between the copper electro-chemical deposition (ECD) and the chemical-mechanical polishing (CMP). This step corresponds to a partial CMP step (pre-CMP) and is applied after ECD and before anneal in order to modify the copper overburden thickness. Depending on the targeted thickness, copper grain growth occurs during anneal with different efficiencies. Crystallization and grain growth behaviour inside wires is investigated with focused ions beam (FIB). We present here our methodology for sample preparation and characterization. Results are focused on electrical variations and on morphological aspects of copper crystallization and grain growth inside lines observed with various overburden thicknesses.     

激光诱导化学液相沉积Fe膜的研究

为了沉积出表面平整、尺寸精确、沉积区域具有可选择性的Fe膜,采用YAG固体激光器,以Fe(CO)5为液相前驱体,利用一定厚度的石英片减少副产物,在激光功率密度为1.0106W/cm2、激光频率为2.5kHz、激光扫描速率为300mm/s、激光重复扫描次数为200次的条件下,沉积出表面平整性较好、并且具有一定厚度的Fe沉积层。通过测试分析发现,沉积层表面质量受激光功率密度影响较大;激光功率密度是影响到沉积层能否沉积以及沉积厚度的重要参量。结果表明,通过激光诱导,以Fe(CO)5为前驱体,可以实现铜表面的Fe膜的沉积。     

High‐efficiency copper indium gallium diselenide (CIGS) solar cells with indium sulfide buffer layers deposited by atomic layer chemical vapor deposition (ALCVD)

This paper presents optimization studies on the formation of indium sulfide buffer layers for high‐efficiency copper indium gallium diselenide (CIGS) thin‐film solar cells with atomic layer chemical vapour deposition (ALCVD) from separate pulses of indium acetylacetonate and hydrogen sulfide. A parametric study of the effect of deposition temperature between 160° and 260°C and thickness (15–30 nm) shows an optimal value at about 220°C for a layer thickness of 30 nm, leading to an efficiency of 16·4%. Analysis of the device shows that indium sulfide layers are characterised by an improvement of the blue response of the cells compared with a standard CdS‐processed cell, due to a high apparent band gap (2·7–2·8 eV), higher open‐circuit voltages (up to 665 mV) and fill factor (78%). This denotes high interface quality. Atomic diffusion processes of sodium and copper in the buffer layer are demonstrated. Copyright © 2003 John Wiley & Sons, Ltd.     

Copper metallization for advanced IC: requirements and technological solutions

Due to the scaling down, the contribution of interconnects should become preponderant for the performance of IC. The use of low-k dielectrics and/or low resistivity metals in order to decrease the parasitic capacitance of interconnect is a technological requirement. Especially the use of copper, with mineral dielectric as IMD, instead of aluminium alloy is now commonly accepted. In this paper we compare the intrinsic performance of two damascene architectures. The planarization by metal CMP, which will determine the final metal thickness, may induce killer defects (shorts between lines) or degraded metal sheet resistance uniformity for multi-level metallization devices. The impact on electromigration of the damascene structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent. On the other hand, the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition.     

Atomic layer chemical vapour deposition of copper

Copper films with (1 1 1) texture are of crucial importance in integrated circuit interconnects. We have deposited strongly (1 1 1)-textured thin films of copper by atomic layer deposition (ALD) using [2,2,6,6-tetramethyl-3,5-heptadionato] Cu(II), Cu(thd)₂, as the precursor. The dependence of the microstructure of the films on ALD conditions, such as the number of ALD cycles and the deposition temperature was studied by X-ray diffraction, scanning electron microscopy (SEM), and transmission electron microscopy. Analysis of (1 1 1)-textured films shows the presence of twin planes in the copper grains throughout the films. SEM shows a labyrinthine structure of highly connected, large grains developing as film thickness increases. This leads to low resistivity and suggests high resistance to electromigration.