A comparison between BIMOS device types

This paper deals with the design and comparison of three types of BIMOS transistors (cascade, cascode, and parallel combinations of MOSFET and bipolar transistors). The first section of the paper presents a technique for accurately determining the overall deviceI-Vrelations for the cascade (Darlington) combination based on the area ratio for the MOSFET and bipolar transistors. From this, one sees that the optimum area ratio varies from 1.5 for 700-V devices to 0.2 for 80- V devices. The second section of the paper deals with the design and comparison of the cascode and parallel device types. In these cases, no optimum area ratio based solely on device conduction exists and the device design and comparison is based on achieving the maximum current density limited by keeping the power dissipation to under 100 W/ cm². Included in this analysis are losses due to conduction as well as switching. The results show that a 0.5 area ratio (MOSFET to bipolar transistor) is optimum for the cascode (series) combination and a 0.3 ratio is a good compromise for the parallel combination. The last section of the paper shows an overall comparison of all of the BIMOS device types together with the MOSFET and the bipolar transistor.     

Epitaxial V-groove bipolar integrated circuit process

A new four-mask "V-groove" process for the fabrication of bipolar integrated circuits has been developed. The process utilizes epitaxial ν/n⁺/n^-layers and anisotropic etching oflangle100ranglesilicon to eliminate the buried layer and isolation diffusions as well as the need for masking the base diffusion of the standard six-mask bipolar integrated circuit process, n-p-n transistor, resistor, and Schottky diode characteristics are equivalent to or exceed those of the standard process. A five-mask V-groove process provides improved lateral p-n-p transistors compared with the four-mask approach. The V-groove integrated circuit structure offers simpler processing, smaller isolation capacitances, lower parasitic collector resistances, larger packing densities, and higher junction breakdown voltages than standard bipolar integrated circuits without degradation of other properties.     

Bipolar structures for BIMOS technologies

Recent advances in LSI and VLSI have offered many possibilities in mixing MOSFET and bipolar integrated structures on the same chip. The authors study the integration of bi-polar structures in BIMOS environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology, e.g., the nonexistence of an n/SUP +/ underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip, and uses the epitaxial (substrate) resistance as a load. It can be used to realize logic and memory functions. Computer simulation as well as experimental results show that the structure can perform efficiently in both BIMOS and bipolar technologies.     

A SPICE compatible subcircuit model for lateral bipolar transistorsin a CMOS process

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 μm CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJT's)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction     

A CMOS model for computer-aided circuit analysis and design

An equivalent circuit model to simulate the current-voltage behavior of CMOS transistors is discussed. This model can simulate the full range of complementary MOSFET operation and can handle latchup at the circuit analysis level. Using effective injection efficiencies a switching criterion and a method of solution for a four parasitic bipolar transistor system have been developed and incorporated. The configuration of the CMOS device is computed from data submitted by the user. This includes well depth, MOSFET separation, doping levels, minority-carrier lifetime, substrate bypass resistors, the option to float either or both substrates, and bias conditions. The model can be used alone or incorporated into existing computer-aided-design programs for analysis of circuits which contain CMOS components     

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25-μm base width have been successfully fabricated in a p-well 0.25-μm bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported     

New insulated-gate thyristor structure with MOSFET coupled baseregions

A new insulated-gate thyristor (IGTH) structure in which the base of n-p-n transistor is coupled to the base of p-n-p transistor through a MOSFET is described for the first time, In the new structure, called base coupled insulated gate thyristor (BC-IGTH), the parasitic lateral p-n-p carrier injection inherent in previously reported thyristor structures such as the MCT, BRT, and IGTH is absent. The absence of parasitic lateral p-n-p carrier injection results in low on state voltage drop and high controllable current capability for this structure. The turn-on process in the new structure is fundamentally different from other MOS-gated thyristor structures in that in the new structure, the higher gain n-p-n transistor is turned-on first, which then provides the base drive for the lower gain p-n-p transistor. Multicellular 800 V devices of the new thyristor structure were fabricated using a double-diffused DMOS process, and were found to give on-state drop of 1.1 V at 200 A/cm², and controllable currents in excess of 100 A/cm² were obtained by forming MOS-gate controlled emitter-to-base resistive shorts     

Simulating single-event burnout of n-channel power MOSFET's

Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs     

Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation

Substrate current injection effects are one of the major risks for smart-power IC functionality, often leading to redesigns. Smart-power ICs for motor control consist of four power transistors in H-bridge configuration and the controlling circuitry on a single chip. During switching of the power stages driving an inductive load (e.g. a motor), parasitic bipolar transistors turn on and inject electrons and holes into the substrate. This leads to a substrate potential shift with the risk of disturbing the functionality of the controlling circuitry or even triggering a latch-up. The substrate potential shift due to minority carrier injection by the lateral parasitic NPN transistor has been measured on a test chip and analyzed by 3D device simulation. The previously calibrated 3D device simulation and the measurements are in good agreement. The influence of protecting measures (substrate contacts) and the backside contact has been investigated experimentally. For the first time, the potential shift due to the parasitic substrate NPN transistor has been measured and simulated in 3D on an entire chip.     

Devices and circuits for bipolar (V)LSI

It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit. General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor fT, and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes. Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design. Logic circuits (such as I²L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed.     

Parasitic transistor effects in CMOS VLSI

Parasitic field-effect transistor (FETs) and bipolar junction transistors (BJTs) in a CMOS circuit are described, along with their interactions with each other and their effect on circuit performance. The results are considered to be useful for setting up design rules between n-channel and p-channel active transistors in CMOS IC layout. Novel parasitic transistors associated with next-generation VLSI technologies, such as trench isolation and silicon-on-insulator, are discussed briefly     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

The injection model-a structure-oriented model for merged transistor logic (MTL)

The merged transistor device is represented by assigning separate diodes to the various electron and hole injections along the active p-n junction. Where collection takes place, current sources are introduced. Measurement procedures are described that allow a quantitative separation of the various injections, and hence the determination of the model parameters. Results of such measurements are given. Device terminal parameters, like current gains and storage time constants, can be predicted from the measurements for devices of arbitrary horizontal geometry, so that the injection model can serve as a device optimization tool. As a circuit analysis model it allows representation of the internal device series resistances which would not be possible with an Ebers-Moll model. The injection model is significant beyond the merged transistor logic (MTL) aspects as it renders a better insight into bipolar devices, particularly into lateral p-n-p and saturated n-p-n transistors.     

A switching lateral transistor

A switching phenomenon has been reported in certain lateral geometry transistors in silicon integrated circuits. These devices switch between conducting and nonconducting states at a critical value of VCE. A hypothesis for the mechanism has been proposed. In this paper an equivalent circuit is developed for the switching lateral transistor and is used to predict transistor behavior. The effect of manufacturing tolerances on the device switching voltage is investigated and a technique of production control is proposed. Circuits using the device are described in which the circuit switching voltage may be varied over a wide range. Some applications of the switching lateral transistor, as an overvoltage protection circuit and a relaxation oscillator, are described.     

A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

A new dynamic random access memory cell using a bipolar MOS composite structure

A new dynamic random access memory (RAM) cell which incoperates an n-p-n bipolar junction transistor with an n-channel MOSFET in a composite structure, is proposed and investigated. In this novel cell called the BIMOS cell, the collector-base junction serves as a buried storage capacitor whereas the n-MOSFET as a transfer gate. The fabrication technology is simple and compatible with that of single-polysilicon CMOS IC's and a minimum cell size of 14.875F²with a minimum feature sizeFis realizable. The write, read, and standby operations of the cell are analyzed and simulated. An experimental cell is fabricated and characterized. Dynamic test is successfully performed. The investigation on the cell performance is also made. It has shown that large storage capacitance to bit-line capacitance ratio as well as fairly good packing density, soft-error immunity and leakage characteristics are expected. Furthermore, as compared to the conventional 1-transistor cell the new cell can be scaled down with less processing troubles and better performance improvements. Simple process and good scaled-down properties offer great potential for the proposed new cell to be used in the design of larger dynamic MOS RAM's.     

A compact model for multiterminal bipolar devices used in smartpower applications

Complex technologies merging low-voltage bipolar devices and vertical current-flow power transistor allow more smart functions at low chip cost but pose problems during the design phase because there is no way to predict the influence of the high-voltage transistor over the control components by using standard bipolar junction transistor (BJT) models. In fact the large inductive load usually present in high-voltage power transistors applications forces both negative substrate voltage and spurious currents that can induce positive feedback among parasitic devices, downgrading the performance of a single device and so of the whole circuit. In this work we introduce a model for the five-terminal bipolar devices used in smart power applications. The model accounts for all main static and dynamic parasitic effects and gives results in very good agreement with experimental data on both simple devices and complex integrated circuits currently implemented in commercial products for microprocessor based engine management systems (EMS's)     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Consideration of the frequency performance potential of GaAs homojunction and heterojunction n-p-n transistors

A study is made of the expected frequency performance of n-p-n GaAs homojunction transistors and n-p-n AlGaAs-GaAs heterojunction transistors. The analysis suggests that if parasitic base resistance is minimized in the homojunction transistor design, the frequency performance should be comparable to that of heterojunction transistors of similar dimensions.     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated