应用于DVB电视调谐器的低相位噪声数控晶体振荡器设计

本文提出了一种全集成的25-MHz数字控制晶体振荡器。该数控晶体振荡器基于Colpitts结构实现。通过自动幅度控制电路实现相位噪声的优化。通过10位的温度计译码电容阵列实现自动频率控制。测试结果表明,该数控晶体振荡器在1kHz和10kHz频偏处的相位噪声分别为–139 dBc/Hz和–151 dBc/Hz。频率调谐范围约为35ppm,频率精度为0.04ppm。该数控晶体振荡器在SMIC 0.18μm CMOS工艺下实现,电源电压1.8V,消耗电流1mA。     

A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners

This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator(DCXO) with automatic amplitude control(AAC).The DCXO is based on Colpitts topology for one-pin solution.The AAC circuit is introduced to optimize the phase noise performance.The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array,ensuring a～35 ppm tuning range and～0.04 ppm frequency step.The measured phase noise results are-139 dBc/Hz at 1 kHz and-151 dBc/Hz at 10 k...     

A portable digitally controlled oscillator using novel varactors

This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The proposed DCO with novel DCV can be implemented with standard cells, and thus it can be ported to different processes in short time. Furthermore, the final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to 1.55 ps with standard 0.35-/spl mu/m 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, high portability, and short design turnaround cycle compared with conventional DCO designs.     

A digitally programmable switched-capacitor universal active filter/oscillator

A universal second-order switched-capacitor filter section has been fabricated on an NMOS chip. The device can perform all five basic filter types as well as a sine wave oscillator without external components, while requiring only an external clock. The filter type is determined by selecting one or more of three input pins. The filter response is determined by ten external programming pins which may be either digitally controlled or hard wired.     

A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.     

A portable high-frequency digitally controlled oscillator (DCO)

A novel digitally-controlled oscillator (DCO) is reported. Utilizing a new capacitive load, the new DCO is capable of producing much higher output frequencies than existing DCOs. All other components are fully digital and modular, allowing portability to any CMOS process and customization for different applications. At the heart of the DCO is a digital ring oscillator (DRO) that utilizes the new shunt-capacitive loads. Unprecedented higher frequencies are obtained through a novel idea of electrically removing the effect of un-enabled loads. Simple design conditions for achieving proper operation of the DRO are provided and verified through simulations with several technologies. Spice simulations verified the correct and superior operation of the DCO even with device mismatch. A custom layout of the DRO was generated using LFoundry's 150 nm technology. The total DRO area was found to be 418 µm². Comparison with other DCOs and VCO shows that the new DCO outperforms conventional DCOs in all aspects; maximum attainable frequency, power efficiency and required number of control bits to achieve a certain resolution.     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

基于自由环振和飞加法器结构的时域数字控制振荡器

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.     

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

t supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.     

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.     

一种带振幅调节的晶体振荡器

设计了一种带振幅控制的晶体振荡器,用于32 768 Hz的实时时钟.振幅调节环采用源接地振荡器形式来得到高的频率稳定性和低的功耗.使用MOS管电阻有效的减小了版图面积.电路在0.35 μm、5 V CMOS工艺上实现,仿真和测试结果都能满足设计要求.     

A low-current Al-gate C-MOS crystal oscillator

The subthreshold properties of MOS transistors have been used advantageously to implement a crystal oscillator that operates at the sub-microampere current levels, using low-voltage metal-gate C-MOS technology. Composed of a reference current generator, a voltage-amplitude regulator, a Pierce oscillator, and an a.c. amplifier, the circuit can be put into a shutdown mode for power conservation.     

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator(DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18μm CMOS process with six metal layers.A third new way to change capacitance is proposed and implemented in this work.Results show that the phase noise at 1 MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also,the DCO can work at low supply voltage conditions with a 1.6 ...     

一种基于新型电容阵列的低功耗低相位噪声数字控制振荡器

摘要： 利用0.18CMOS六层金属工艺实现了一个全集成的低功耗低相位噪声的数字控制振荡器,该数字控制振荡器谐振回路由中央抽头对称螺旋电感和电容阵列构成。文中介绍并实现了一种新型的改变电容的方法。该方法在不需要改变接入谐振回路电容的数量而通过改变其互联拓扑关系来实现。测试结果表明,在1.8V电源电压下,核心模块消耗4.8mA的电流,相位噪声在1MHz频偏处为-122.5dBc/Hz。在1.6V的低电源电压,消耗约4mA的电流情况下,1MHz频偏处相位噪声仍可达到-121.5dBc/Hz. 同时,电源推挽度小于10MHz/V。     

TD-TTL crystal oscillator

The crystal oscillator constructed on the basis of Deng's (1979) RC oscillator with a tunnel diode and a TTL inverter has excellent characteristics, such as : high speed, wide band of working frequencies, sine and pulse waveforms at the output. The consideration of the oscillations condition and the measured characteristics of the circuit are given.     

All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator

This work presented a 150–450-MHz, all-digital phase-locked loop (ADPLL) implemented in a 0.18 μm CMOS process. The design utilizes bulk-controlled varactor and pulse-based digitally controlled oscillator (PB-DCO) providing a high timing resolution and a good jitter performance. The worst-case total locking time of the proposed ADPLL is 32 reference clock cycles. The divider used here divides by factors from 2 to 63. A test chip is implemented and verified. The RMS and peak-to-peak jitters are 6.7 and 44 ps, respectively, at 450-MHz. The peak-to-peak jitter is 2.0% at 450-MHz. When the multiplication of divider is varying at 150-MHz, the peak-to-peak jitters are less than 3.2%. The power consumption is 16.2-mW at 450-MHz. The core area of ADPLL is only 260 × 360 mm². This clock generator can be applied as re-usable silicon IP for system-on-chip (SoC) applications.     

A one-pin crystal oscillator for VLSI circuits

The oscillator features the same stability, reliability, and ease of use as the common Pierce oscillator; however, only one package pin and no external components other than the crystal need be dedicated to the oscillator. The design is quite general, and may be implemented in either NMOS or CMOS technologies, using only a moderate amount of silicon area. Design examples are given, and the fabrication results are presented.     

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.     

MOS crystal oscillator design

The operation of MOS crystal oscillators is investigated assuming near-sinusoidal AC voltages at gate and drain. It is shown that the circuit operation depends basically on only two normalized parameters. Computer solution is used to produce a series of normalized curves allowing oscillator design for prescribed start-up conditions, steady-state amplitude, and operating current. The theoretical predictions agree closely with measurements on sample circuits.