低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor

This paper presents a new CMOS transconductor providing low distortion for rail-to-rail signals. The circuit is based on using the anti-phase common source topology with the floating current source to extend its linearity range. The difference in the biasing currents of the floating current source is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for applications requiring wide dynamic ranges. Rail-to-rail operation is achieved with THD less than –37 dB. The bandwidth achieved by the transconductor is 67.5 MHz using a supply voltage of ±1.5 V.     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

A highly linear CMOS buffer amplifier

A CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described. The buffer operates from a 5-V supply, is capable of rail-to-rail operation at both the input and output, an exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 /spl Omega/ at 20 kHz.     

Active series switch for switched-opamp circuits

A series switch to be used in switched-opamp circuits is proposed. The circuit can be implemented in standard CMOS technology and allows rail-to-rail input and output signals to be processed without a voltage multiplier. Using a 0.5 μm CMOS technology, with a 1 V supply, the circuit exhibits a total harmonic distortion better than -60 dB for a differential signal amplitude up to 1.8 Vpp     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

A 75 μW rail-to-rail class AB CMOS operational amplifier

A new class AB CMOS operational amplifier featuring rail-to-rail output swing is presented. The proposed circuit operates with an output voltage supply of 1 V only, while the overall power consumption is lower than 75 μW. The output stage shows a quiescent current of 15 μA, while it guarantees a peak current of 220 μA. The slew rate is 1.5 V μs⁻¹ (C₁ = 150 pF) and the THD is −63 dB, when a 0.98 V_pp−10.4 kHz sinewave is applied, as measured on an experimental prototype realised with a standard 0.8 μm CMOS process. The circuit presented is suitable for use in portable hand-set systems or in medical aids.     

A novel class of complementary folded-cascode opamps for low voltage

Three novel complementary folded-cascode operational amplifiers (opamps) with high gain, large bandwidth, and rail-to-rail input range for low-voltage operation will be presented. These opamps feature high bandwidth due to minimum internal nodes. The output swing is increased by properly adjusting the output cascode transistor gate voltages close to the power supply voltages. The opamps have been fabricated with a standard 0.8-/spl mu/m CMOS technology. Measurements show the amplification is between 60.1 and 72.4 dB, and the unity gain bandwidth is 14 MHz for a 5-pF load, 2.5-V power supply, and 150-/spl mu/A bias current.     

A high-linearity 50-Ω CMOS differential driver for ISDNapplications

A CMOS differential line-driver amplifier that uses positive feedback in the input stage to give transconductance multiplication and pole-zero doublet insertion is reported. The gain-bandwidth product at 60 kHz is 30 MHz and the unity-gain frequency is 2.7 MHz. The circuit operates from a single 5-V power supply and can achieve a total harmonic distortion (THD) of -78 dB for a 6-V_pp differential output signal at 40 kHz and for a load of 100 Ω and/or 150 pF. For the same measuring condition but with a load of 50 Ω and/or 150 pF, the THD is -73 dB. A power supply rejection of more than 76 dB up to 150 kHz was obtained. The chip occupies an area of 1200 mil² in a 1.5-μm CMOS technology and dissipates 20 mW     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

一种输入输出轨到轨CMOS运算放大器的设计

随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18 μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 mV到电源电压减去50 mV,实现了输入输出轨到轨的目标。     

A CMOS low-distortion fully differential power amplifier withdouble nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology     

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented. The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion. The improved Miller OTA has been successfully verified in a standard 0.35-mum CMOS process. Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.     

CMOS buffer using complementary pair of bulk-driven super source followers

A power-efficient rail-to-rail CMOS analogue voltage buffer is presented. It consists of a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilised to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 mum CMOS technology to operate at a 1.8 V supply voltage. Simulated results are provided to demonstrate the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68 pF load is as low as -46 dB, while the static current consumption remains under 8 muA.     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage

Two 3.3-V operational amplifiers with constant-g _m rail-to-rail input stage and rail-to-rail output stage are presented. The constant transconductance (g _m ) ensures a constant unity-gain frequency within the whole commonmode input range. Two new methods to control theg _m are introduced. Both operational amplifiers use the same rail-to-rail output stage. The operational amplifiers have been integrated in a CMOS semicustom process with transistor lengths of 10µm. The common-mode input voltage swing extends beyond the positive supply rail by 400 mV and beyond the negative supply rail by 200 mV. The output voltage is able to reach within 130 mV of the supply rails. The output current of the operational amplifiers is 2 mA and the voltage gain is 85 dB. The unity-gain frquency is 165 kHz, which is mainly limited by the relatively long transistor lengths of 10µm. In another process with channel lengths of 2µm, simulation results showed that a unity-gain frequency of 4 MHz can easily be obtained.     

A current mode feed-forward gain control system for a 0.8 V CMOS hearing aid

A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly improves the total harmonic distortion（THD）by digital gain control.To attain the digital gain control codes according to the extremely weak output signal from the microphone,a rectifier and a state controller implemented in current mode are proposed.A prototype chip has been designed based on a 0.13μm standard CMOS process.The measurement results show that the supply voltage can be as low as 0.6 V.And with the 0.8 V supply voltage,the THD is improved and below 0.06%（-64 dB）at the output level of 500 mV_p-p,yet the power consumption is limited to 40μW.In addition,the input referred noise is only 4μV_rmsand the maximum gain is maintained at 33 dB.